Einzeltreffer — DigiBib

A method and a phase locked loop (PLL) circuit for implementing compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO). The PLL circuit includes a reference circuit generates a virtual ground node for biasing noise sensitive components, providing level shifted VCO increment and decrement tuning values from a phase detector coupled by a respective resistor to tune a varactor of the LC VCO, and providing a loop filter function. The virtual ground node tracks a logic power supply noise, incurring no jitter penalty, and eliminating the need for a separate power supply for the PLL circuit.

Titel:	Implementing compact current mode logic (CML) inductor capacitor (LC) voltage controlled oscillator (VCO) for high-speed data communications
Autor/in / Beteiligte Person:	International Business Machines Corporation
Link:	View record in USPTO Patent Grants (Volltext)
Veröffentlichung:	2015
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Grants Sprachen: English Patent Number: 8,994,460 Publication Date: March 31, 2015 Appl. No: 13/675650 Application Filed: November 13, 2012 Assignees: International Business Machines Corporation (Armonk, NY, US) Claim: 1. A method for implementing a compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications comprising: providing a PLL circuit including a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO); providing a reference circuit generating a virtual ground node for biasing noise sensitive components using a logic power supply, said virtual ground node tracking logic power supply noise, incurring no jitter penalty; and using said virtual ground node for providing level shifted VCO increment and decrement tuning values from a phase detector for tuning said CML LC VCO, and providing a loop filter function. Claim: 2. The method as recited in claim 1 wherein providing the PLL circuit including a reference circuit generating a virtual ground node for biasing noise sensitive components includes providing the reference circuit generating the virtual ground node including a decoupling capacitor connected between the virtual ground node and logic power supply rail. Claim: 3. The method as recited in claim 2 wherein said decoupling capacitor includes a small decoupling capacitor having a capacitance value of about 5 pico-farad (pF). Claim: 4. The method as recited in claim 2 includes providing a series connected pair of field effect transistors coupled between the logic power supply rail and the virtual ground node and a current source connected to a virtual regulator reference. Claim: 5. The method as recited in claim 1 wherein providing a PLL circuit including a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO) includes providing an LC tank resonator including an inductor and voltage-controlled capacitance varactors receiving the level shifted increment and decrement tuning signals through a respective resistor for tuning said CML LC VCO. Claim: 6. The method as recited in claim 5 includes said respective resistor and said voltage-controlled capacitance varactors providing said loop filter function. Claim: 7. A phase locked loop (PLL) circuit for implementing a compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications comprising: a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO); said LC VCO including an inductor and voltage-controlled capacitance varactors; a reference circuit generating a virtual ground node for biasing noise sensitive components, said virtual ground node tracking a logic power supply noise, incurring no jitter penalty; a feedback frequency divider receiving a VCO oscillation signal from said CML LC VCO and providing a divided down feedback frequency signal to a phase detector; a level shifter coupled to said phase detector including said virtual ground node providing level shifted VCO increment and decrement tuning values coupled by a respective resistor to said voltage-controlled capacitance varactors for tuning said voltage-controlled capacitance varactors of the LC VCO, and providing a loop filter function. Claim: 8. The phase locked loop (PLL) circuit as recited in claim 7 includes a calibration macro function calibrating a center frequency of said CML LC VCO at power on. Claim: 9. The phase locked loop (PLL) circuit as recited in claim 7 wherein said reference circuit generating the virtual ground node includes a decoupling capacitor connected between the virtual ground node and logic power supply rail. Claim: 10. The phase locked loop (PLL) circuit as recited in claim 9 wherein said decoupling capacitor includes a small decoupling capacitor having a capacitance value of about 5 pico-farad (pF). Claim: 11. The phase locked loop (PLL) circuit as recited in claim 9 includes a series connected pair of field effect transistors coupled between the logic power supply rail and the virtual ground node, and a current source to a virtual regulator reference. Claim: 12. The phase locked loop (PLL) circuit as recited in claim 7 wherein said CML LC VCO includes an AC coupled level shifter receiving a VCO oscillation signal and providing a virtual ground node level shifted VCO frequency signal and a second level shifter shifting back to said VCO oscillation signal applied to said feedback frequency divider. Claim: 13. The phase locked loop (PLL) circuit as recited in claim 7 wherein said phase detector includes a quadrature XOR phase detector; said quadrature XOR phase detector outputs VCO increment and decrement tuning signals separated in phase by 90 degrees. Claim: 14. The phase locked loop (PLL) circuit as recited in claim 7 wherein said LC VCO includes a cross coupled differential pair of field effect transistors coupled between said inductor and voltage-controlled capacitance varactors and a current source. Claim: 15. A design structure embodied in a machine readable medium used in a design process, the design structure comprising: a phase locked loop (PLL) circuit tangibly embodied in the machine readable medium used in the design process, said PLL circuit for implementing a compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications, said PLL circuit comprising: a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO); said LC VCO including an inductor and voltage-controlled capacitance varactors; a reference circuit generating a virtual ground node for biasing noise sensitive components, said virtual ground node tracking a logic power supply noise, incurring no jitter penalty; a feedback frequency divider receiving a VCO oscillation signal from said CML LC VCO and providing a divided down feedback frequency signal to a phase detector; a level shifter coupled to said phase detector including said virtual ground node providing level shifted VCO increment and decrement tuning values coupled by a respective resistor to said voltage-controlled capacitance varactors for tuning said voltage-controlled capacitance varactors of the LC VCO, and providing a loop filter function, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said PLL circuit. Claim: 16. The design structure of claim 15 , wherein the design structure comprises a netlist, which describes said PLL circuit. Claim: 17. The design structure of claim 15 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits. Claim: 18. The design structure of claim 15 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications. Claim: 19. The design structure of claim 15 , wherein said reference circuit generating the virtual ground node includes a decoupling capacitor connected between the virtual ground node and logic power supply rail, and a series connected pair of field effect transistors coupled between the logic power supply rail and the virtual ground node, and a current source connected to a virtual regulator reference. Claim: 20. The design structure of claim 15 , wherein said LC VCO includes cross coupled differential pair of field effect transistors coupled between said inductor and said voltage-controlled capacitance varactors and a current source; and wherein said PLL circuit includes a calibration macro function calibrating a center frequency of said CML LC VCO at power on. Current U.S. Class: 331/17 Patent References Cited: 6127880 October 2000 Holst et al. ; 6943636 September 2005 Moore ; 7498888 March 2009 Nitsche et al. ; 7667545 February 2010 Schlueter et al. ; 2003/0076177 April 2003 Fischer ; 2010/0277245 November 2010 Liu Assistant Examiner: Shin, Jeffrey Primary Examiner: Chang, Joseph Attorney, Agent or Firm: Pennington, Joan

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Implementing compact current mode logic (CML) inductor capacitor (LC) voltage controlled oscillator (VCO) for high-speed data communications