Einzeltreffer — DigiBib

A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Titel:	Method of manufacturing semiconductor device with offset sidewall structure
Autor/in / Beteiligte Person:	Renesas Electronics Corporation
Link:	View record in USPTO Patent Grants (Volltext)
Veröffentlichung:	2016
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Grants Sprachen: English Patent Number: 9,349,816 Publication Date: May 24, 2016 Appl. No: 14/931000 Application Filed: November 03, 2015 Assignees: RENESAS ELECTRONICS CORPORATION (Koutou-ku, JP) Claim: 1. A semiconductor device including a first n-type MISFET formed in a first region of a semiconductor substrate, a first p-type MISFET formed in a second region of the semiconductor substrate, a second n-type MISFET formed in a third region of the semiconductor substrate and having a thicker gate insulating film than that of the first n-type MISFET, and a second p-type MISFET formed in a fourth region of the semiconductor substrate and having a thicker gate insulating film than that of the first p-type MISFET, comprising: a first gate insulating film formed over the first region; a second gate insulating film formed over the second region; a first gate electrode formed over the first gate insulating film; a second gate electrode formed over the second gate insulating film; a first n-type impurity region formed in the first region; a second n-type impurity region formed in the first region and having a higher impurity concentration than the first n-type impurity region; a first p-type impurity region formed in the second region; and a second p-type impurity region formed in the second region and having a higher impurity concentration than the first p-type impurity region, wherein first insulating films are formed over a side surface of the first gate electrode and over a side surface of the second gate electrode; wherein second insulating films are formed over the side surface of the first gate electrode and over the side surface of the second gate electrode through the first insulating films; wherein third insulating films are formed over the side surface of the first gate electrode and over the side surface of the second gate electrode through the first and second insulating films; wherein the first n-type impurity region is formed by introducing first impurities in self alignment with the first insulating film formed in the first region, wherein the first p-type impurity region is formed by introducing second impurities in self alignment with the second insulating film formed in the second region, wherein the second n-type impurity region is formed by introducing third impurities in self alignment with the third insulating film formed in the first region, wherein the second p-type impurity region is formed by introducing fourth impurities in self alignment with the third insulating film formed in the second region, wherein a first silicide film is formed on the second n-type impurity region and is formed in self alignment with the third insulating film, wherein a second silicide film is formed on the second p-type impurity region and is formed in self alignment with the third insulating film, wherein the second insulating film is a spacer state, and wherein the third insulating film is a spacer state. Claim: 2. A semiconductor device according to the claim 1 , wherein an edge of the first n-type impurity region is located under the first gate electrode, and wherein an edge of the first p-type impurity region is located under the second gate electrode. Claim: 3. A semiconductor device according to the claim 1 , wherein a p-type pocket region is formed in the first region and is formed by introducing fifth impurities in self alignment with the first insulating film. Claim: 4. A semiconductor device according to the claim 1 , wherein an n-type pocket region is formed in the second region and is formed by introducing sixth impurities in self alignment with the second insulating film. Claim: 5. A semiconductor device according to the claim 1 , wherein the first insulating film includes a silicon oxide film. Claim: 6. A semiconductor device according to the claim 1 , wherein the second insulating film includes a silicon oxide film. Claim: 7. A semiconductor device according to the claim 1 , wherein the third insulating film includes a silicon nitride film. Claim: 8. A semiconductor device including a first MISFET of a first conductive type formed in a first region of a semiconductor substrate, a second MISFET of a second conductive type opposite to the first conductive type formed in a second region of the semiconductor substrate, a third MISFET of the first conductive type formed in a third region of the semiconductor substrate and having a thicker gate insulating film than that of the first MISFET, and a fourth MISFET of the second conductive type formed in a fourth region of the semiconductor substrate and having a thicker gate insulating film than that of the second MISFET, comprising: a first gate insulating film formed over the first region: a second gate insulating film formed over the second region; a first gate electrode formed over the first gate insulating film; a second gate electrode formed over the second gate insulating film; a first impurity region of the first conductive type formed in the first region; a second impurity region of the first conductive type formed in the first region and having a higher impurity concentration than the first impurity region; a third impurity region of the second conductive type formed in the second region; and a fourth impurity region of the second conductive type formed in the second region and having a higher impurity concentration than the third impurity region, wherein first, second and third insulating films are formed over a side surface of the first gate electrode and over a side surface of the second gate electrode in order; wherein the first impurity region includes first impurities which are introduced by using the first insulating film formed in the first region as a mask, wherein the second impurity region includes second impurities which are introduced by using the second insulating film formed in the second region as a mask, wherein the third impurity region includes third impurities which are introduced by using the third insulating film formed in the first region as a mask, wherein the fourth impurity region includes fourth impurities which are introduced by using the third insulating film formed in the second region as a mask, wherein a first silicide film is formed on the third impurity region and is formed by using the third insulating film as a mask, wherein a second silicide film is formed on the fourth impurity region and is formed by using the third insulating film as a mask, wherein the second insulating film is a spacer state, and wherein the third insulating film is a spacer state. Claim: 9. A semiconductor device according to the claim 8 , wherein an edge of the first impurity region is located under the first gate electrode, and wherein an edge of the second impurity region is located under the second gate electrode. Claim: 10. A semiconductor device according to the claim 8 , wherein a first pocket region of the second conductive type is formed in the first region and includes fifth impurities which are introduced by using the first insulating film as a mask. Claim: 11. A semiconductor device according to the claim 8 , wherein a second pocket region of the first conductive type is formed in the second region and includes sixth impurities which are introduced by using the second insulating film as a mask. Claim: 12. A semiconductor device according to the claim 8 , wherein the first insulating film includes a silicon oxide film. Claim: 13. A semiconductor device according to the claim 8 , wherein the second insulating film includes a silicon oxide film. Claim: 14. A semiconductor device according to the claim 8 , wherein the third insulating film includes a silicon nitride film. Patent References Cited: 5405791 April 1995 Ahmad et al. ; 6217357 April 2001 Masuoka ; 6380021 April 2002 Wang et al. ; 6492218 December 2002 Mineji ; 6569742 May 2003 Taniguchi et al. ; 6614684 September 2003 Shukuri et al. ; 7531402 May 2009 Ota et al. ; 2001/0019641 September 2001 Ikeda et al. ; 2002/0006054 January 2002 Shukuri et al. ; 2002/0163080 November 2002 Taniguchi et al. ; 2010/0190354 July 2010 Burnett et al. ; 64-84659 March 1989 ; 3-58430 March 1991 ; 6-216151 August 1994 ; 6-268165 September 1994 ; 9-167804 June 1997 ; 9-172176 June 1997 ; 2000-269357 September 2000 ; 2001-110913 April 2001 Other References: H. Sayama, et al. “80nm CMOSFET Technology Using Double Offset-Implanted Source/Drain Extension and Low Temperature SIN Process” IEEE 2000, 4 pages. cited by applicant ; Japanese Office Action issued Jan. 25, 2011 in Patent Application No. 2001-288918 (with partial English-language translation). cited by applicant ; Office Action issued Jan. 15, 2013 in Japanese Application No. 2011-060369 (w/partial English language translation). cited by applicant ; Office Action mailed Apr. 23, 2013 in Japanese Application No. 2011-060369 (w/partial English translation). cited by applicant Primary Examiner: Pham, Thanh V Attorney, Agent or Firm: Oblon, McClelland, Maier & Neustadt, L.L.P

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Method of manufacturing semiconductor device with offset sidewall structure