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- Nachgewiesen in: USPTO Patent Grants
- Sprachen: English
- Patent Number: 10964,362
- Publication Date: March 30, 2021
- Appl. No: 16/393997
- Application Filed: April 25, 2019
- Assignees: Marvell Asia Pte, Ltd. (Singapore, SG)
- Claim: 1. A memory cell comprising: a first storage node configured to store a bit of data; a first read pass-gate transistor and a first read pull-down transistor connected in series between a common read bitline and a first voltage rail, wherein a gate of the first read pass-gate transistor is connected to a first read wordline, and wherein a gate of the first read pull-down transistor is connected to the first storage node; a second storage node configured to store a one's complement of the bit of data; a second read pass-gate transistor and a second read pull-down transistor connected in series between the common read bitline and the first voltage rail, wherein a gate of the second read pass-gate transistor is connected to a second read wordline, and wherein a gate of the second read pull-down transistor is connected to the second storage node; a capacitor connected to the common read bitline and controlling a discharge rate of the common read bitline to prevent a voltage level on the common read bitline from fully discharging to a ground reference voltage level during stepping down of the voltage level on the common read bitline; a first write pass-gate transistor connected to the first storage node; and a second write pass-gate transistor connected to the second storage node, wherein a gate of the first write pass-gate transistor and a gate of the second write pass-gate transistor are connected to a same write wordline for concurrent write access to the first storage node and the second storage node.
- Claim: 2. The memory cell of claim 1 , wherein: during a read operation to accomplish an XNOR operation, the common read bitline is pre-charged and a read pulse is applied selectively to only one of the first read wordline and the second read wordline; and during the read pulse applied, digital inputs for the XNOR operation performed by the memory cell are logic states of the first read wordline and the bit of data is stored at the first storage node, and an output of the XNOR operation performed by the memory cell is determinable based on whether discharging of the voltage level on the common read bitline of the memory cell occurs.
- Claim: 3. The memory cell of claim 2 , wherein: when both the first read wordline and the bit of data have a same logic state, the discharging of the voltage level on the common read bitline of the memory cell occurs and indicates the output of the XNOR operation is a high logic state; and when the first read wordline and the bit of data have different logic states, the discharging of the voltage level on the common read bitline of the memory cell is prevented and indicates the output of the XNOR operation is a low logic state.
- Claim: 4. The memory cell of claim 2 , wherein: the memory cell is incorporated into a memory array configured for in-memory computing of binary neural network operations; and the logic states of the first read wordline and the bit of data correspond to a binary input value and a binary weight value.
- Claim: 5. The memory cell of claim 1 , further comprising: the first voltage rail implemented as a ground rail or a negative voltage rail; a second voltage rail implemented as a positive voltage rail; a pair of cross-coupled inverters connected between the first voltage rail and the second voltage rail and comprising a first inverter and a second inverter; and a pair of complementary bitlines comprising a first bitline and a second bitline, wherein the first inverter comprises the first storage node, the second inverter comprises the second storage node, the first write pass-gate transistor is connected between the first storage node and the first bitline, and the second write pass-gate transistor is connected between the second storage node and the second bitline.
- Claim: 6. A memory array comprising memory cells arranged in columns and rows of the memory array, wherein: each column of the memory array comprises a common read bitline, a voltage comparator connected to the common read bitline, and a capacitor connected to the common read bitline and controlling a discharge rate of the common read bitline to prevent an actual voltage level on the common read bitline from fully discharging to a ground reference voltage level during stepping down of the actual voltage level on the common read bitline; each row of the memory array comprises a first read wordline, and a second read wordline; and each of the memory cells comprises a first storage node configured to store a bit of data, a first read pass-gate transistor and a first read pull-down transistor connected in series between a first voltage rail and the common read bitline of one of the columns including the memory cell of the first storage node, a gate of the first read pass-gate transistor is connected to the first read wordline for a row including the memory cell of the first storage node, and a gate of the first read pull-down transistor is connected to the first storage node, a second storage node configured to store a one's complement of the bit of data, a second read pass-gate transistor and a second read pull-down transistor connected in series between the common read bitline of the one of the columns and the first voltage rail, a gate of the second read pass-gate transistor is connected to the second read wordline of the row, and a gate of the second read pull-down transistor is connected to the second storage node.
- Claim: 7. The memory array of claim 6 , further comprising bitline drivers and wordline drivers, wherein: during concurrent read operations of all of the memory cells in a selected one of the columns to accomplish concurrent XNOR operations, a bitline driver pre-charges the common read bitline and the capacitor of the selected one of the columns; the wordline drivers selectively apply read pulses to only one of the first read wordline and the second read wordline in each of the rows; following the read pulses, the voltage comparator of the selected one of the columns compares the actual voltage level on the common read bitline for the selected one of the columns to a reference voltage level and generates a digital output; the actual voltage level on the common read bitline is indicative of a bit count of results of the concurrent XNOR operations performed by the memory cells in the selected one of the columns; and the reference voltage level corresponds to a bit count threshold such that the digital output indicates whether the bit count is below the bit count threshold.
- Claim: 8. The memory array of claim 7 , wherein, for an XNOR operation performed by each of the memory cells in the selected one of the columns: digital inputs are provided as logic states of the first read wordline connected to one of the memory cells, and the bit of data stored at the first storage node of the one of the memory cells and an output of the XNOR operation performed by the one of the memory cells is determinable based on whether discharging of the actual voltage level on the common read bitline of the selected one of the columns of the one of the memory cells occurs.
- Claim: 9. The memory array of claim 8 , wherein: when both the first read wordline connected to the one of the memory cells and the bit of data have a same logic state, the discharging of the actual voltage level on the common read bitline of the one of the memory cells occurs and indicates the output of the XNOR operation of the one of the memory cells is a high logic state; and when the first read wordline, connected to the one of the memory cells, and the bit of data have different logic states, the discharging of the actual voltage level on the common read bitline of the one of the memory cells is prevented and indicates the output of the XNOR operation of the one of the memory cells is a low logic state.
- Claim: 10. The memory array of claim 6 , wherein: the memory array further comprises bitline drivers and wordline drivers; during concurrent read operations of the memory cells in the columns of the memory array and to accomplish concurrent XNOR operations, the bitline drivers pre-charge the common read bitlines and the capacitors, and the wordline drivers selectively apply read pulses to only one of the first read wordline and the second read wordline in each of the rows; following the read pulses, voltage comparators connected to different common read bitlines of different columns perform compare operations; each of the compare operations performed by one of the voltage comparators, connected to one of the common read bitlines in one of the columns, comprises comparing the actual voltage level on the one of the common read bitlines to a reference voltage level and outputting a digital output; the actual voltage level on the one of the common read bitlines is indicative of a bit count of results of the concurrent XNOR operations performed by the memory cells in the one of the columns; and the reference voltage level corresponds to a bit count threshold such that the digital output of the one of the voltage comparators for the one of the columns indicates whether the bit count is below the bit count threshold.
- Claim: 11. The memory array of claim 10 , wherein: the memory array is configured for in-memory parallel computing of binary neural network operations; and the concurrent XNOR operations performed by the memory cells in the columns of the memory array occur in one clock cycle with logic states of first read wordlines corresponding to binary input values from a first receptive field, with logic states of bits stored in the memory cells of the columns corresponding to binary weight values from different kernels associated with different features, respectively, and with digital outputs from the voltage comparators of the columns being inserted into feature maps for the different features at a same location corresponding to the particular receptive field.
- Claim: 12. The memory array of claim 11 , wherein the concurrent XNOR operations performed by the memory cells in the columns of the memory array are repeated during subsequent clock cycles such that: at each subsequent clock cycle logic states of the first read wordlines correspond to different binary input values from a second receptive field, wherein the second receptive field is different than the first receptive field; the logic states of the bits stored in the memory cells of the columns continue to correspond to binary weight values from the different kernels associated with the different features, respectively; and the digital outputs from the voltage comparators of the columns are inserted into the feature maps for the different features at a location corresponding to the second receptive field.
- Claim: 13. The memory array of claim 6 , wherein each of the memory cells further comprises: a pair of cross-coupled inverters connected between the first voltage rail and a second voltage rail and comprising a first inverter and a second inverter; a first write pass-gate transistor; and a second write pass-gate transistor, wherein the first voltage rail implemented as a ground rail or a negative voltage rail; the second voltage rail implemented as a positive voltage rail; the first inverter comprises the first storage node; the second inverter comprises the second storage node; the first write pass-gate transistor is connected between the first storage node and a first bitline of a pair of complementary bitlines for a corresponding one of the columns; the second write pass-gate transistor is connected between the second storage node and a second bitline of the pair of complementary bitlines; and a gate of the first write pass-gate transistor and a gate of the second write pass-gate transistor are both connected to a write wordline for a corresponding one of the rows.
- Claim: 14. The memory array of claim 6 , wherein: the memory cells are implemented in an active device layer on an integrated circuit chip; and the capacitors connected respectively to the common read bitlines, wherein the capacitors comprise metal-on-metal capacitors.
- Claim: 15. A method comprising: providing a memory array comprising memory cells arranged in columns and rows of the memory array, wherein each of the columns of the memory array comprise a common read bitline, a voltage comparator connected to the common read bitline, and a capacitor connected to the common read bitline, wherein each of the rows of the memory array comprise a first read wordline and a second read wordline, wherein each of the memory cells comprises a first storage node configured to store a bit of data, a first read pass-gate transistor and a first read pull-down transistor connected in series between the common read bitline for one of the columns including the memory cell and a first voltage rail, a second storage node configured to store a one's complement of the bit of data, and a second read pass-gate transistor and a second read pull-down transistor connected in series between the common read bitline for the one of the columns and the first voltage rail, wherein a gate of the first read pass-gate transistor and a gate of the first read pull-down transistor are connected to the first read wordline of one of the rows including the memory cell and to the first storage node, respectively, and wherein a gate of the second read pass-gate transistor and a gate of the second read pull-down transistor are connected to the second read wordline for the one of the rows and to the second storage node, respectively; pre-charging the common read bitline and the capacitor of at least one selected column and selectively applying read pulses to only one of the first read wordline and the second read wordline in each of the rows such that concurrent XNOR operations are performed by memory cells in the at least one selected column; controlling a discharge rate of the common read bitline via the capacitor to prevent an actual voltage level of the common read bitline from fully discharging to a ground reference voltage level during stepping down of the actual voltage level of the common read bitline; and performing a comparison of the actual voltage level on the common read bitline of the at least one selected column to a reference voltage level and outputting a digital output, wherein the actual voltage level on the common read bitline of the at least one selected column is indicative of a bit count of results of the concurrent XNOR operations performed by the memory cells in the at least one selected column, and wherein the reference voltage level corresponds to a bit count threshold such that the digital output indicates whether the bit count is below the bit count threshold.
- Claim: 16. The method of claim 15 , wherein, for an XNOR operation performed by one of the memory cells in the at least one selected column, digital inputs are provided as logic states of the first read wordline connected to the one of the memory cells, and the bit of data stored at the first storage node of the one of the memory cells; and an output of the XNOR operation performed by the one of the memory cells in the at least one selected column is determinable based on whether discharging of the actual voltage level on the common read bitline of the at least one selected column through the one of the memory cells occurs.
- Claim: 17. The method of claim 16 , wherein: when both the first read wordline connected to the one of the memory cells and the bit of data have a same logic state, the discharging of the actual voltage level on the common read bitline through the one of the memory cells occurs and indicates the output of the XNOR operation is a high logic state, and when the first read wordline connected to the one of the memory cells and the bit of data have different logic states, the discharging of the actual voltage level on the common read bitline through the one of the memory cells is prevented and indicates the output of the XNOR operation is a low logic state.
- Claim: 18. The method of claim 15 , wherein: the pre-charging further comprises pre-charging common read bitlines and capacitors of the columns of the memory array such that the read pulses selectively applied to only one of the first read wordline and the second read wordline in each of the rows causes the concurrent XNOR operations to be performed by the memory cells in the columns of the memory array; and the method further comprises concurrently performing comparisons of actual voltage levels on the common read bitlines of the columns to the reference voltage level and outputting digital outputs for each of the columns, respectively.
- Claim: 19. The method of claim 18 , wherein: the method enables in-memory computing of binary neural network operations; and the concurrent XNOR operations performed by the memory cells in the columns of the memory array occur in one clock cycle with logic states of first read wordlines corresponding to binary input values from a first receptive field, with logic states of bits stored in the memory cells of the columns corresponding to binary weight values from different kernels associated with different features, respectively, and with digital outputs from voltage comparators of the columns being inserted into different feature maps for the different features at a same location corresponding to the particular receptive field.
- Claim: 20. The method of claim 19 , wherein: the concurrent XNOR operations performed by the memory cells in the columns of the memory array are repeated during subsequent clock cycles such that at each subsequent clock cycle logic states of the first read wordlines correspond to different binary input values from a second receptive field different than the first receptive field; the logic states of the bits stored in the memory cells of the columns continue to correspond to binary weight values from the different kernels associated with the different features, respectively; and the digital outputs from the voltage comparators of the columns are inserted into the different feature maps for the different features at a location corresponding to the different receptive field.
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- Primary Examiner: Yoha, Connie C
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