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- Nachgewiesen in: USPTO Patent Grants
- Sprachen: English
- Patent Number: 11138,499
- Publication Date: October 05, 2021
- Appl. No: 16/147176
- Application Filed: September 28, 2018
- Assignees: Intel Corporation (Santa Clara, CA, US)
- Claim: 1. An apparatus, comprising: a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip, the CIM circuit comprising a mathematical computation circuit coupled to a memory array, the mathematical computation circuit comprising a switched capacitor circuit, the switched capacitor circuit comprising a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip.
- Claim: 2. The apparatus of claim 1 wherein the memory array comprises a static random access memory (SRAM) memory array.
- Claim: 3. The apparatus of claim 2 wherein the BEOL capacitor and thin film transistor are located above the SRAM memory array.
- Claim: 4. The apparatus of claim 3 wherein the mathematical computation circuit is to accumulate values read from the memory array.
- Claim: 5. The apparatus of claim 3 wherein the mathematical computation circuit is to multiply and accumulate values read from the memory array.
- Claim: 6. The apparatus of claim 1 wherein the mathematical computation circuit is to accumulate values read from the memory array.
- Claim: 7. The apparatus of claim 1 wherein the mathematical computation circuit is to multiply and accumulate values read from the memory array.
- Claim: 8. An apparatus, comprising: a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip, the CIM circuit comprising a mathematical computation circuit coupled to a memory array, the mathematical computation circuit comprising an accumulation circuit, the accumulation circuit comprising a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.
- Claim: 9. The apparatus of claim 8 wherein the memory array comprises a static random access memory (SRAM) memory array.
- Claim: 10. The apparatus of claim 9 wherein the ferroelectric BEOL capacitor is located above the SRAM memory array.
- Claim: 11. The apparatus of claim 10 wherein the mathematical computation circuit is to accumulate values read from the memory array.
- Claim: 12. The apparatus of claim 10 wherein the mathematical computation circuit is to multiply and accumulate values read from the memory array.
- Claim: 13. The apparatus of claim 8 wherein the mathematical computation circuit is to accumulate values read from the memory array.
- Claim: 14. The apparatus of claim 8 wherein the mathematical computation circuit is to multiply and accumulate values read from the memory array.
- Claim: 15. The apparatus of claim 8 wherein ferroelectric material of the ferroelectric BEOL capacitor comprises grain sizes less than 3 nm and/or is amorphous.
- Claim: 16. The apparatus of claim 8 wherein the ferroelectric BEOL capacitor comprises material selected from the group consisting of: hafnium zirconium oxide; hafnium oxide; zirconium oxide; hafnium aluminum oxide; hafnium silicon oxide; hafnium zirconium aluminum oxide; hafnium zirconium silicon oxide; hafnium yttrium oxide; yttrium zirconium oxide; hafnium yttrium zirconium oxide.
- Claim: 17. The apparatus of claim 16 wherein the material is doped with yttrium.
- Claim: 18. The apparatus of claim 8 wherein the CIM circuit further comprises a switched capacitor circuit that comprises a circuit to sense a switch in dipole moment direction of the ferroelectric capacitor, wherein, the sense of the switch is to determine an accumulate value.
- Claim: 19. The apparatus of claim 18 wherein the circuit is a current sensing circuit.
- Patent References Cited: 2017/0117041 April 2017 Hamdioui et al. ; 2017/0162105 June 2017 Kim ; 2018/0075339 March 2018 Ma et al. ; 2018/0157970 June 2018 Henry et al.
- Other References: Ambrogio, S., et al., “Equivalent-Accuracy Accelerated Neural-Network Training Using Analogue Memory,” Nature, vol. 558, Jun. 7, 2018, 22 pages. cited by applicant ; Biswas, A., et al., “A 42pJ/decision 3.12TOPS/W Robust In-Memory Machine Learning Classifier With On-Chip Training,” 2018 IEEE International Solid-State Circuits Conference—(ISSCC), San Francisco, CA, 2018, pp. 488-490. cited by applicant ; Fick, D., et al., “Analog Computation in Flash Memory for Datacenter-Scale AI Inference in a Small Chip”, 2.05 Mythic Hot Chips, 2018, 28 pages. cited by applicant ; Gonugondla, S.K., et al., “A 42pJ/decision 3.12TOPS/W Robust In-Memory Machine Learning Classifier With On-Chip Training,” 2018 IEEE International Solid-State Circuits Conference—(ISSCC), San Francisco, CA, 2018, pp. 490-492. cited by applicant ; Henzler, S., “Chapter 2, Time-to-Digital Converter Basics”, Springer Series in Advanced Microelectronics 29, 2, Springer Science+Business Media B.V. 2010. cited by applicant ; Mason, A., “Memory Basics”, Michigan State, ECE 410, Chapter 13 Lecture Notes, pp. 13.1-13.34, 2010. cited by applicant ; Solanki, Umang, “How does SRAM work?”, https://www.quora.com/How-does-SRAM-work, Aug. 17, 2017, 2 pages. cited by applicant ; Stone, Harold S. “A Logic-In-Memory Computer”, IEEE Transactions on Computers, Jan. 1970, 6, pages. cited by applicant ; Zhang, J., et al., “In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array,” in IEEE Journal of Solid-State Circuits, vol. 52, No. 4, 10 pages, Apr. 2017. cited by applicant ; International Search Report and Written Opinion for PCT Patent Application No. PCT/US2019/47774, dated Dec. 18, 2019, 9 pages. cited by applicant ; Chang, Mu-Tien, et al., “Technology Comparison for Large Last-Level Caches (L3Cs): Low-Leakage SRAM, Low Write-Energy STT-RAM, and Refresh-Optimized eDRAM”, HPCA 2013. cited by applicant ; Kang, Mingu, et al., “An In-Memory VLSI Architecture for Convolutional Neural Networks”, http://ieee-cas.org/pubs/ietcas, Published Version DOI: 10.1109/JETCAS.2018.2829522, Publication Apr. 23, 2018, IEEE Circuits and Systems Society, 13 pages. cited by applicant ; Kim, Han Joon, “Gain Size Engineering for Ferroelectric Hf0.5Zr0.5O2 Films by an Insertion of AI203 Interlayer”, Applied Physics Letters 105, 192903 (2014), 6 pages. cited by applicant ; Lun, Sang “Ferroelectricity in Nanocrystalline Hf0.5Zr0.5O2 Thin Films”, Lund University Master Thesis, Nanoelectronics Group, Department of Electrical and Information Technology, LTH, Feb. 26, 2018, 52 pages. cited by applicant ; Materlik, R., et al., “The Origin of Ferroelectricity in Hfxzr1-xO: A computational Investigation and a Surface Energy Model”, Journal of Applied Physics 117, 134109 (2015), 50 pages. cited by applicant ; Meinerzahagen, P., Gain-Cell Embedded DRAMs for Low-Power VLSI, Chapter 2, Gain-Cell eDRAMs (GC-eDRAMs): Review of Basics and Prior Art. cited by applicant ; Park, Min Hyuk,et al., “Evolution of Phase and Ferroelectric Properties of Thin Hf0.5 Zr0.5O2 Films According to the Thickness and Annealing Temperature”, Applied Physics Letters 102, 242905 (2013), 5 pages. cited by applicant ; Pesic, Milan, et al., “A Computational Study of Hafnia Based Ferroelectric Memories: From Ab-initio via Physical Modeling to Circuit Models of Ferroelectric Device”, Journal of computational Electronics, Aug. 2017, 24 pages. cited by applicant ; Schroeder, Uwe, et al., “Ferroelectricity in Doped Hafnium Oxide”, ISA, State College, Conference Paper, May 15, 2014, 41 pages. cited by applicant ; Sunimura, H., et al., “Overview and Future Challenges eDRAM Technologies”, Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, Yokohama, 2006 2 pages. cited by applicant
- Primary Examiner: Movva, Amar
- Attorney, Agent or Firm: Compass IP Law PC
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