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- Nachgewiesen in: USPTO Patent Grants
- Sprachen: English
- Patent Number: 11176,991
- Publication Date: November 16, 2021
- Appl. No: 17/084779
- Application Filed: October 30, 2020
- Assignees: QUALCOMM Incorporated (San Diego, CA, US)
- Claim: 1. A compute-in-memory (CIM) circuit, comprising: a bit line; a static random access memory (SRAM) bit cell circuit, comprising: a storage circuit, comprising: a true inverter circuit comprising a true inverter input node and a true inverter output node comprising a true storage node; and a complement inverter circuit comprising a complement inverter input node coupled to the true inverter output node, and a complement inverter output node comprising a complement storage node coupled only to the true inverter input node; and an access circuit coupled to the true storage node; and a multiplication circuit comprising a first multiplication input node coupled to the storage circuit, a second multiplication input node, and a multiplication output node; the multiplication circuit configured to generate on the multiplication output node, a multiplication product of a first multiplication input on the first multiplication input node and a second multiplication input on the second multiplication input node.
- Claim: 2. The CIM circuit of claim 1 , further not comprising a second access circuit coupled to the complement storage node.
- Claim: 3. The CIM circuit of claim 2 , further not comprising a second bit line coupled to the SRAM bit cell circuit.
- Claim: 4. The CIM circuit of claim 1 , wherein the multiplication circuit comprises an exclusive OR (XOR)-based circuit configured to generate the multiplication product on the multiplication output node as an XOR-based logic operation of the first multiplication input and the second multiplication input.
- Claim: 5. The CIM circuit of claim 4 , wherein: the first multiplication input node comprises: a first true multiplication input node coupled to the true storage node and configured to receive true storage data on the true storage node; and a first complement multiplication input node coupled to the complement storage node and configured to receive complement storage data on the complement storage node; the second multiplication input node comprises: a second true multiplication input node configured to receive a second true multiplication input data; and a second complement multiplication input node configured to receive a second complement multiplication input data; and the XOR-based circuit comprises: a first multiplication transistor, comprising: a first source/drain coupled to the first true multiplication input node; a first drain/source coupled to the multiplication output node; and a first gate coupled to the second true multiplication input node; and a second multiplication transistor, comprising: a second source/drain coupled to the first complement multiplication input node; a second drain/source coupled to the multiplication output node; and a second gate coupled to the second complement multiplication input node.
- Claim: 6. The CIM circuit of claim 4 , wherein: the first multiplication input node comprises: a first true multiplication input node coupled to the true storage node and configured to receive true storage data on the true storage node; and a first complement multiplication input node coupled to the complement storage node and configured to receive complement storage data on the complement storage node; the second multiplication input node comprises: a second true multiplication input node configured to receive a second true multiplication input data; and a second complement multiplication input node configured to receive a second complement multiplication input data; and the XOR-based circuit comprises: a first multiplication transistor, comprising: a first source/drain coupled to the second true multiplication input node; a first drain/source coupled to the multiplication output node; and a first gate coupled to the first true multiplication input node; and a second multiplication transistor, comprising: a second source/drain coupled to the second complement multiplication input node; a second drain/source coupled to the multiplication output node; and a second gate coupled to the first complement multiplication input node.
- Claim: 7. The CIM circuit of claim 1 , further comprising a non-volatile (NV) capacitor circuit coupled to the multiplication output node.
- Claim: 8. The CIM circuit of claim 7 , wherein the NV capacitor circuit comprises a ferroelectric capacitor circuit.
- Claim: 9. The CIM circuit of claim 1 , wherein: the bit line is configured to be pre-charged to a pre-charge voltage; and the access circuit is configured to pass a data value on the true storage node to the bit line in response to the access circuit being activated.
- Claim: 10. The CIM circuit of claim 1 , further comprising: a first supply voltage rail coupled to the true inverter circuit, the first supply voltage rail configured to receive a first supply voltage; and a second supply voltage rail coupled to the complement inverter circuit, the second supply voltage rail configured to receive a second supply voltage; the second supply voltage rail configured to provide a boosted voltage based on the second supply voltage in response to the access circuit being activated to perform an access operation to the SRAM bit cell circuit, the boosted voltage exceeding the first supply voltage.
- Claim: 11. The CIM circuit of claim 1 , further comprising: a first positive supply voltage rail configured to receive a first positive supply voltage; a second positive supply voltage rail configured to receive a second positive supply voltage; a first negative supply voltage rail configured to receive a first ground voltage; and a second negative supply voltage rail configured to receive a second ground voltage; wherein the true inverter circuit comprises: a true positive (P)-type field-effect transistor (FET) (PFET), comprising: a true P-type source coupled to the first positive supply voltage rail; a true P-type gate coupled to the complement inverter output node, and a true P-type drain coupled to the complement inverter input node; and a true negative (N)-type FET (NFET), comprising: a true N-type drain coupled to the first negative supply voltage rail; a true N-type gate coupled to the complement inverter output node; and a true N-type source coupled to the complement inverter input node; and the complement inverter circuit comprises: a complement PFET, comprising: a complement P-type source coupled to the second positive supply voltage rail; a complement P-type gate coupled to the true inverter output node; and a complement P-type drain coupled to the true inverter input node; and a complement NFET, comprising: a complement N-type drain coupled to the second negative supply voltage rail; a complement N-type gate coupled to the true inverter output node; and a complement N-type source coupled to the true inverter input node.
- Claim: 12. The CIM circuit of claim 11 , wherein the second positive supply voltage rail is coupled to the first positive supply voltage rail.
- Claim: 13. The CIM circuit of claim 11 , wherein: the second positive supply voltage rail is configured to provide a positive boosted voltage based on the second positive supply voltage in response to the access circuit being activated to perform an access operation to the SRAM bit cell circuit, the positive boosted voltage exceeding the first positive supply voltage; and the second negative supply voltage rail is configured to provide a negative boosted voltage based on the second ground voltage in response to the access circuit being activated to perform the access operation to the SRAM bit cell circuit, the negative boosted voltage negatively exceeding the first ground voltage.
- Claim: 14. The CIM circuit of claim 1 , wherein the SRAM bit cell circuit is a five-transistor (5T) SRAM bit cell circuit.
- Claim: 15. The CIM circuit of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
- Claim: 16. The CIM circuit of claim 1 integrated in an integrated circuit (IC).
- Claim: 17. A method of performing a compute-in-memory (CIM) operation, comprising: activating an access circuit to couple a bit line to a true storage node of a true inverter circuit of a static random access memory (SRAM) bit cell circuit, the SRAM bit cell circuit comprising: the true inverter circuit comprising a true inverter input node and a true inverter output node comprising the true storage node; and a complement inverter circuit comprising a complement inverter input node coupled to the true inverter output node, and a complement inverter output node comprising a complement storage node coupled only to the true inverter input node; providing a true data value from the true storage node as a first multiplication input to a first multiplication input node of a multiplication circuit; asserting a second multiplication input to a second multiplication input node of the multiplication circuit; and generating a multiplication product on a multiplication output node of the multiplication circuit based on a multiplication of the first multiplication input and the second multiplication input.
- Claim: 18. The method of claim 17 , further comprising: providing a first positive supply voltage of a first positive supply voltage rail to the true inverter circuit; providing a second positive supply voltage of a second positive supply voltage rail to the complement inverter circuit; and positively boosting the second positive supply voltage to exceed the first positive supply voltage in response to the access circuit being activated.
- Claim: 19. The method of claim 18 , further comprising: providing a first ground voltage of a first negative supply voltage rail to the true inverter circuit; providing a second ground voltage of a second negative supply voltage rail to the complement inverter circuit; and negatively boosting the second ground voltage to negatively exceed the first ground voltage in response to the access circuit being activated.
- Claim: 20. The method of claim 17 , further comprising: providing a memory domain supply voltage to a memory array in a processor-based system; providing a first supply voltage to the true inverter circuit less than the memory domain supply voltage; and providing a second supply voltage to the complement inverter circuit.
- Claim: 21. The method of claim 20 , further comprising pre-charging the bit line to the first supply voltage.
- Claim: 22. A memory system, comprising: a compute-in-memory (CIM) array circuit comprising a plurality of CIM circuits each comprising: a static random access memory (SRAM) bit cell circuit, comprising: a storage circuit, comprising: a true inverter circuit comprising a true inverter input node and a true inverter output node comprising a true storage node; and a complement inverter circuit comprising a complement inverter input node coupled to the true inverter output node, and a complement inverter output node comprising a complement storage node coupled only to the true inverter input node; and an access circuit coupled to the true storage node; and a multiplication circuit comprising a first multiplication input node coupled to the storage circuit, a second multiplication input node, and a multiplication output node; the multiplication circuit configured to generate on the multiplication output node, a multiplication product of a multiplication of a first multiplication input on the first multiplication input node and a second multiplication input on the second multiplication input node; a first bit line coupled to each of the access circuits of a first subset of the plurality of CIM circuits; a second bit line coupled to each of the access circuits of a second subset of the plurality of CIM circuits different from the first subset of the plurality of CIM circuits; and a bit line driver circuit coupled to the first bit line and the second bit line; the bit line driver circuit configured to: pre-charge the first bit line to a first pre-charge voltage of true read data; and pre-charge the second bit line to a second pre-charge voltage of complement read data.
- Claim: 23. The memory system of claim 22 , wherein the bit line driver circuit is physically located in the CIM array circuit between a first end CIM circuit among the first subset of the plurality of CIM circuits and a second end CIM circuit among the second subset of the plurality of CIM circuits.
- Claim: 24. The memory system of claim 22 , wherein: a number of CIM circuits in the first subset of the plurality of CIM circuits is equal to a number of CIM circuits in the second subset of the plurality of CIM circuits; the first subset of the plurality of CIM circuits is arranged in a first linear array; the second subset of the plurality of CIM circuits is arranged in a second linear array aligned with the first linear array; and the bit line driver circuit is physically located in an area between the first linear array and the second linear array.
- Claim: 25. The memory system of claim 22 , wherein: the CIM array circuit further comprises a global bit line (GBL); and each of the multiplication output nodes of the plurality of CIM circuits in the CIM array circuit is coupled to the GBL.
- Claim: 26. The memory system of claim 25 , wherein the CIM array circuit further comprises a global bit line driver circuit configured to pre-charge the GBL to a pre-charge voltage.
- Claim: 27. The memory system of claim 26 , further comprising a memory array, wherein: the memory array is configured to receive a memory domain supply voltage; and the global bit line driver circuit is configured to pre-charge the GBL to the pre-charge voltage less than the memory domain supply voltage.
- Patent References Cited: 2019/0088310 March 2019 Li
- Primary Examiner: Hoang, Huan
- Attorney, Agent or Firm: Qualcomm Incorporated
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