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Interconnects having a portion without a liner material and related structures, devices, and methods

INTEL, CORPORATION
2022
Online Patent

Titel:
Interconnects having a portion without a liner material and related structures, devices, and methods
Autor/in / Beteiligte Person: INTEL, CORPORATION
Link:
Veröffentlichung: 2022
Medientyp: Patent
Sonstiges:
  • Nachgewiesen in: USPTO Patent Grants
  • Sprachen: English
  • Patent Number: 11264,325
  • Publication Date: March 01, 2022
  • Appl. No: 16/628991
  • Application Filed: September 28, 2017
  • Assignees: Intel Corporation (Santa Clara, CA, US)
  • Claim: 1. An integrated circuit (IC) structure, comprising: an interlayer dielectric (ILD) material having an uppermost surface; an interconnect comprising electrically conductive material and including a first portion proximate to a first end of the interconnect and a second portion proximate to a second end of the interconnect, the first end extending to or into the ILD material and the second end opposite the first end; and a liner material around the first portion of the interconnect and between the first end of the interconnect and the ILD material, wherein an end of the liner material opposite the first end of the interconnect defines a boundary between the first portion of the interconnect and the second portion of the interconnect, wherein the boundary is above the uppermost surface of the ILD material.
  • Claim: 2. The IC structure of claim 1 , further comprising a remnant of a hermetic liner material in contact with the ILD material and adjacent to at least part of the first portion of the interconnect, wherein the liner material is between the interconnect and the ILD material and between the interconnect and the remnant of the hermetic liner material.
  • Claim: 3. The IC structure of claim 2 , wherein a thickness of the remnant of the hermetic liner material is about two nanometers (2 nm).
  • Claim: 4. The IC structure of claim 2 , wherein the remnant of the hermetic liner material includes HfO 2 , Al 2 O 3 , carbon doped SiN, or combinations thereof.
  • Claim: 5. The IC structure of claim 1 , wherein a distance from the second end of the interconnect to the first portion of the interconnect is about eighty percent (80%) of a total length of the interconnect from the first end to the second end.
  • Claim: 6. The IC structure of claim 1 , further comprising an air gap adjacent to the second portion of the interconnect.
  • Claim: 7. The IC structure of claim 6 , further comprising an encapsulation material adjacent to the second end of the interconnect and configured to encapsulate the air gap.
  • Claim: 8. The IC structure of claim 1 , further comprising a replacement ILD material adjacent to the second portion of the interconnect.
  • Claim: 9. The IC structure of claim 8 , wherein a replacement dielectric constant of the replacement ILD material is less than a dielectric constant of the ILD material.
  • Claim: 10. The IC structure of claim 9 , wherein the replacement dielectric constant is between about 1.9 and 2.1, and the dielectric constant is between about 2.9 and 3.5.
  • Claim: 11. A method of manufacturing an integrated circuit (IC) structure, the method comprising: removing an interlayer dielectric (ILD) material from between interconnects that are at least partially covered with a liner material to expose a portion of the liner material that covers a second portion of the interconnects; applying a conformal hermetic liner to a remaining ILD material and the exposed portion of the liner material; applying a carbon hard mask (CHM) between the interconnects; removing a portion of the CHM to a distance from the remaining ILD; removing the conformal hermetic liner from the exposed portion of the liner material to a remaining portion of the CHM; and removing the exposed portion of the liner material to the remaining portion of the CHM to expose the second portion of the interconnects.
  • Claim: 12. The method of claim 11 , wherein removing an ILD material from between interconnects comprises removing the ILD material using a dry etch to form air gaps between the interconnects.
  • Claim: 13. The method of claim 11 , wherein removing an ILD material from between interconnects comprises exposing a portion of the liner material that covers about eighty percent (80%) of a length of the interconnects.
  • Claim: 14. The method of claim 11 , wherein applying a conformal hermetic liner comprises depositing about two nanometers (2 nm) of the conformal hermetic liner.
  • Claim: 15. The method of claim 11 , wherein applying a conformal hermetic liner comprises applying at least one material selected from the group consisting of HfO 2 , Al 2 O 3 , and carbon doped SiN.
  • Claim: 16. The method of claim 11 , wherein applying a CHM comprises spinning on the CHM.
  • Claim: 17. The method of claim 11 , wherein removing a portion of the CHM comprises etching the CHM back to the distance from the remaining ILD.
  • Claim: 18. The method of claim 11 , wherein removing the conformal hermetic liner comprises etching the hermetic liner using wet etch chemistry.
  • Claim: 19. The method of claim 11 , wherein removing the exposed portion of the liner material comprises etching the exposed portion with a piranha etch.
  • Claim: 20. The method of claim 11 , further comprising encapsulating air gaps between the exposed second portion of the interconnects with an encapsulation material.
  • Claim: 21. The method of claim 11 , further comprising filling gaps between the exposed second portion of the interconnects with a replacement ILD.
  • Claim: 22. A computing device comprising: at least one integrated circuit (IC) structure including: a plurality of interconnects, each having a first portion at a first end thereof covered with a liner material and a second portion at a second end thereof without the liner material; a hermetic liner between the first portion of the interconnects; and an interlayer dielectric (ILD) proximate at least part of the liner material at the first end of each of the plurality of interconnects.
  • Claim: 23. The computing device of claim 22 , further comprising: a processor mounted on a substrate; a memory unit capable of storing data; a graphics processing unit; an antenna within the computing device; a display on the computing device; a battery within the computing device; a power amplifier within the processor; and a voltage regulator within the processor; wherein at least one of the processor, the memory unit, the graphics processing unit, the antenna, the display, the battery, the power amplifier, and the voltage regulator comprises the at least one IC structure.
  • Claim: 24. An integrated circuit (IC) structure, comprising: an interlayer dielectric (ILD) material; an interconnect comprising electrically conductive material and including a first portion proximate to a first end of the interconnect and a second portion proximate to a second end of the interconnect, the first end extending to or into the ILD material and the second end opposite the first end; a liner material around the first portion of the interconnect and between the first end of the interconnect and the ILD material, wherein an end of the liner material opposite the first end of the interconnect defines a boundary between the first portion of the interconnect and the second portion of the interconnect; and a remnant of a hermetic liner material in contact with the ILD material and adjacent to at least part of the first portion of the interconnect, wherein the liner material is between the interconnect and the ILD material and between the interconnect and the remnant of the hermetic liner material.
  • Claim: 25. An integrated circuit (IC) structure, comprising: an interlayer dielectric (ILD) material; an interconnect comprising electrically conductive material and including a first portion proximate to a first end of the interconnect and a second portion proximate to a second end of the interconnect, the first end extending to or into the ILD material and the second end opposite the first end; and a liner material around the first portion of the interconnect and between the first end of the interconnect and the ILD material, wherein an end of the liner material opposite the first end of the interconnect defines a boundary between the first portion of the interconnect and the second portion of the interconnect, wherein a distance from the second end of the interconnect to the first portion of the interconnect is about eighty percent (80%) of a total length of the interconnect from the first end to the second end.
  • Claim: 26. An integrated circuit (IC) structure, comprising: an interlayer dielectric (ILD) material; an interconnect comprising electrically conductive material and including a first portion proximate to a first end of the interconnect and a second portion proximate to a second end of the interconnect, the first end extending to or into the ILD material and the second end opposite the first end; a liner material around the first portion of the interconnect and between the first end of the interconnect and the ILD material, wherein an end of the liner material opposite the first end of the interconnect defines a boundary between the first portion of the interconnect and the second portion of the interconnect; and an air gap adjacent to the second portion of the interconnect.
  • Claim: 27. An integrated circuit (IC) structure, comprising: an interlayer dielectric (ILD) material; an interconnect comprising electrically conductive material and including a first portion proximate to a first end of the interconnect and a second portion proximate to a second end of the interconnect, the first end extending to or into the ILD material and the second end opposite the first end; a liner material around the first portion of the interconnect and between the first end of the interconnect and the ILD material, wherein an end of the liner material opposite the first end of the interconnect defines a boundary between the first portion of the interconnect and the second portion of the interconnect; and a replacement ILD material adjacent to the second portion of the interconnect.
  • Patent References Cited: 7488679 February 2009 Standaert ; 9455403 September 2016 Lai et al. ; 2014/0264864 September 2014 Weng et al. ; 2016/0197013 July 2016 Backes et al. ; 3034655 June 2016 ; 1020160014558 February 2016
  • Other References: PCT/US2017/054018, International Search Report and Written Opinion, dated Jun. 21, 2018, 13 pages. cited by applicant
  • Assistant Examiner: Booker, Vicki B.
  • Primary Examiner: Ahmed, Shahed
  • Attorney, Agent or Firm: Schwabe, Williamson & Wyatt, P.C.

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