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- Nachgewiesen in: USPTO Patent Grants
- Sprachen: English
- Patent Number: 11271,011
- Publication Date: March 08, 2022
- Appl. No: 16/924377
- Application Filed: July 09, 2020
- Assignees: Samsung Electronics Co., Ltd. (Gyeonggi-do, KR)
- Claim: 1. A field effect transistor structure comprising: a first FET side and a second FET side region extending in a first direction and spaced apart from each other in a second direction, the second direction crossing the first direction; a first finger and a second finger on the first FET side, the first finger and the second finger extending in the second direction and spaced apart from each other in the first direction; a first source/drain terminal at a side of the first finger; a second source/drain terminal between the first finger and the second finger; a third source/drain terminal at a side of the second finger; a common power net extending in the first direction and connected to the first to third source/drain terminals; and a half double diffusion break (Half-DDB) on the second FET side, the Half-DDB isolating the first and second fingers in the second FET side, wherein the first FET side continuously extends in the first direction.
- Claim: 2. The structure of claim 1 , wherein the first FET side includes a plurality of first fins that are extending in the first direction and are spaced apart from each other in the second direction, and wherein the second FET side includes a plurality of second fins that are extending in the first direction and are spaced apart from each other in the second direction.
- Claim: 3. The structure of claim 2 , wherein the first FET side includes N number of the first fins, and the second FET side includes M number of the second fins, wherein N is different from M, and wherein N and M are integers.
- Claim: 4. The structure of claim 3 , wherein N is greater than M.
- Claim: 5. The structure of claim 1 , wherein the field effect transistor structure is a standard FinFet cell.
- Claim: 6. The structure of claim 1 , further comprising: a cut-poly layer between the first FET side and the second FET side, wherein the cut-poly layer extends in the first direction and is between the half double diffusion break (Half-DDB) and each of the first and second fingers.
- Claim: 7. The structure of claim 1 , wherein the first FET side is a P-type FinFet side, and the second FET side is an N-type FinFet side.
- Claim: 8. A field effect transistor structure comprising: a first FET side and a second FET side extending in a first direction and spaced apart from each other in a second direction, the second direction crossing the first direction a first finger and a second finger on the first FET side, the first finger and the second finger extending in the second direction and spaced apart from each other in the first direction; a first source/drain terminal at a side of the first finger; a second source/drain terminal between the first finger and the second finger; a third source/drain terminal at a side of the second finger; a common internal net on the first FET side, the common internal net connected to the first to third source/drain terminals; and a half double diffusion break (Half-DDB) on the second FET side, the Half-DDB isolating the first and second fingers in the second FET side.
- Claim: 9. The structure of claim 8 , wherein the common internal net overlaps with the first and second fingers.
- Claim: 10. The structure of claim 8 , wherein the first FET side includes a plurality of first fins that are extending in the first direction and are spaced apart from each other in the second direction, and wherein the second FET side includes a plurality of second fins that are extending in the first direction and are spaced apart from each other in the second direction.
- Claim: 11. The structure of claim 10 , wherein the first FET side includes N number of the first fins, and the second FET side includes M number of the second fins, wherein N is different from M, and wherein N and M are integers.
- Claim: 12. The structure of claim 11 , wherein N is greater than M.
- Claim: 13. The structure of claim 8 , wherein the field effect transistor structure is a standard FinFet cell.
- Claim: 14. The structure of claim 13 , wherein the first FET side is a P-type FinFet side, and the second FET side is an N-type FinFet side.
- Claim: 15. The structure of claim 8 , further comprising: a cut-poly layer between the first FET side and the second FET side, wherein the cut-poly layer extends in the first direction.
- Claim: 16. The structure of claim 15 , wherein the cut-poly layer extends between the half double diffusion break (Half-DDB) and each of the first and second fingers.
- Patent References Cited: 7224029 May 2007 Anderson et al. ; 10748932 August 2020 Agarwal ; 2010/0183961 July 2010 Shieh et al. ; 2016/0163716 June 2016 Zhang et al. ; 2016/0211251 July 2016 Liaw ; 2017/0141211 May 2017 Xie ; 2017/0287933 October 2017 Chen et al. ; 2018/0006035 January 2018 Yuan
- Other References: Sheikh, Farhana, et al., “The Impact of Device-Width Quantization on Digital Circuit Design Using FinFET Structures”, EE 241 Spring 2004. cited by applicant ; https://www.synopsys.com/COMPANY/PUBLICATIONS/SYNOPSYSINSIGHT/Pages/Art2-finfet-challenges-ip-lssQ3-12.aspx. cited by applicant ; Joshi, et al. “Mechanical Stress Aware Optimization for Leakage Power Reduction,” IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 29, No. 5, pp. 722-736 (2010). cited by applicant ; Kahng, et al. “Exploiting STI Stress for Performance,” IEEE, pp. 83-90 (2007). cited by applicant ; Lee, et al. “Layout-induced stress effects on the performance and variation of FinFETs,” SISPAD, pp. 369-372 (2015). cited by applicant
- Assistant Examiner: Stevenson, Andre C
- Primary Examiner: Smith, Zandra V
- Attorney, Agent or Firm: Harness, Dickey & Pierce, P.L.C.
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