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- Nachgewiesen in: USPTO Patent Grants
- Sprachen: English
- Patent Number: 11340,685
- Publication Date: May 24, 2022
- Appl. No: 17/159318
- Application Filed: January 27, 2021
- Assignees: SAMSUNG ELECTRONICS CO., LTD. (Suwon-si, KR)
- Claim: 1. A system on chip (SoC) comprising: a plurality of intellectual property (IP) blocks; and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks, one of the IP blocks providing a request signal to the CMU indicating that the one of the IP blocks desires to enter a selected one of a sleep mode and an active mode, wherein the CMU comprises a plurality of clock components forming a parent-child relationship with each other, wherein a parent clock component is configured to transmit a request signal to a child clock component and the child clock component is configured to transmit an acknowledgement signal to the parent clock component; and wherein, in response to the request signal indicating that the one of the IP blocks desires to enter the sleep mode, the CMU is configured to disable a phase locked loop (PLL).
- Claim: 2. The SoC of claim 1 , wherein the CMU is configured to provide an acknowledgement signal to indicate that the CMU has stopped outputting the output clock signal in response to the request signal indicating that the one of the IP blocks desires to enter the sleep mode, and then stops providing the output clock signal to the one of the IP blocks.
- Claim: 3. The SoC of claim 1 , further comprising a power management unit cutting off power to the CMU when no request signals have been sent by the IP blocks during a given period.
- Claim: 4. The SoC of claim 1 , wherein the CMU comprises a controller receiving a first signal from a crystal oscillator and a second signal from the phase locked loop (PLL), and providing one of the received signals as the output clock signal and an acknowledgement signal in response to the request signal.
- Claim: 5. The SoC of claim 1 , wherein the CMU comprises: a multiplexer receiving an internal clock signal and an external clock signal, and providing one of the received clock signals as the output clock signal; and a control circuit providing an acknowledgement signal in response to the request signal.
- Claim: 6. The SoC of claim 1 , wherein the CMU comprises: a frequency dividing circuit dividing an input clock signal to generate a divided clock signal, and providing the divided clock signal as the output clock signal; and a control circuit providing an acknowledgement signal in response to the request signal.
- Claim: 7. The SoC of claim 1 , wherein the CMU comprises: a shortstop circuit performing an operation on an input clock signal to generate a resulting clock signal comprising a plurality of pulses during a first period and a constant level during a second period, and providing the resulting clock signal as the output clock signal; and a control circuit providing an acknowledgement signal in response to the request signal.
- Claim: 8. The SoC of claim 1 , wherein the CMU comprises: a control circuit outputting a control signal and an acknowledgement signal in response to the request signal; and a clock source outputting clock signal in response to the control signal.
- Claim: 9. The SoC of claim 1 , wherein the CMU comprises: a first clock component providing a first request signal indicating that a first one of the IP blocks desires to enter one of a sleep mode and an active mode; a second clock component providing a second request signal indicating that a second one of the IP blocks desires to enter one of a sleep mode and an active mode; and a third clock component to start providing a clock signal to both the first and second clock components when one of the request signals indicate a desire to enter the active mode, and stop providing the clock signal when both of the request signals indicate a desire to enter the sleep mode.
- Claim: 10. The SoC of claim 1 , wherein the CMU comprises: a clock component performing the clock gating; a channel management (CM) circuit managing a channel connecting the CM circuit to the at least one of IP blocks; and a wire connecting the clock component to the CM circuit, wherein the request signal is sent across the wire from the CM circuit to the clock component, and wherein an acknowledgement signal is sent across the wire from the clock component to the CM circuit.
- Claim: 11. A system on chip (SoC) comprising: a plurality of intellectual property (IP) blocks; and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks, one of the IP blocks providing a request signal to the CMU indicating that the one of the IP blocks desires to enter a selected one of a sleep mode and an active mode, wherein the CMU comprises a plurality of clock components connected in a cascade and the plurality of clock components comprise a leaf clock component, at least one middle clock component, and a root clock component; wherein the one of the IP blocks is configured to transmit a request signal to the leaf clock component; wherein each of the plurality of clock components is configured to transmit the request signal to its child clock component and transmit an acknowledgement signal to its parent clock component; and wherein the root clock component is configured to disable a phase locked loop (PLL) in response to receiving the request signal.
- Claim: 12. The SoC of claim 11 , wherein the CMU is configured to provide an acknowledgement signal to indicate the CMU has stopped outputting the output clock signal in response to the request signal indicating that the one of the IP blocks desires to enter the sleep mode, and then stops providing the output clock signal to the one of the IP blocks.
- Claim: 13. The SoC of claim 11 , further comprising a power management unit cutting off power to the CMU when no request signals have been sent by the IP blocks during a given period.
- Claim: 14. The SoC of claim 11 , wherein the root clock component comprises a controller receiving a first signal from a crystal oscillator and a second signal from the phase locked loop (PLL), and providing one of the received signals as the output clock signal and an acknowledgement signal in response to the request signal.
- Claim: 15. The SoC of claim 11 , wherein the at least one middle clock component comprises a multiplexer receiving an internal clock signal and an external clock signal, and providing one of the received clock signals as the output clock signal.
- Claim: 16. The SoC of claim 11 , wherein the at least one middle clock component comprises a frequency dividing circuit dividing an input clock signal to generate a divided clock signal, and providing the divided clock signal as the output clock signal.
- Claim: 17. The SoC of claim 11 , wherein the at least one middle clock component comprises a shortstop circuit performing an operation on an input clock signal to generate a resulting clock signal comprising a plurality of pulses during a first period and a constant level during a second period, and providing the resulting clock signal as the output clock signal.
- Claim: 18. The SoC of claim 11 , wherein the CMU comprises: a control circuit outputting a control signal and an acknowledgement signal in response to the request signal; and a clock source outputting a clock signal in response to the control signal.
- Claim: 19. The SoC of claim 11 , wherein the CMU comprises: a channel management (CM) circuit managing a channel connecting the CM circuit to the one of the IP blocks; and a wire connecting one of the plurality of the clock components to the CM circuit, wherein the request signal is sent across the wire from the CM circuit to the plurality of the clock components, and wherein an acknowledgement signal is sent across the wire from the plurality of the clock components to the CM circuit.
- Claim: 20. The SoC of claim 11 , wherein each of the plurality of the clock components communicates with an adjacent one of the plurality of the clock components using full handshaking.
- Claim: 21. The SoC of claim 20 , wherein the full handshaking comprises a child clock component among the plurality of the clock components outputting a request signal to a parent clock component among the plurality of the clock components and the parent clock component outputting an acknowledgement to the child clock component indicating that the request signal was received.
- Claim: 22. The SoC of claim 21 , wherein the request signal indicates that provision of a clock signal is to be started or stopped.
- Claim: 23. A clock management unit (CMU) comprising: a clock management unit (CMU) comprising: a phase locked loop (PLL); a first clock component comprising a first clock gating circuit; a second clock component comprising a first clock dividing circuit; a third clock component comprising a shortstop circuit; a fourth clock component comprising a second clock dividing circuit; a fifth clock component comprising a multiplexing circuit; and a sixth clock component comprising a PLL controller; wherein an IP block is connected to the CMU and the IP block is configured to transmit a signal to the first clock component; wherein, in response to receiving the signal, the first clock component is configured to disable the first clock gating circuit and transmit the signal to the second clock component; wherein, in response to receiving the signal, the second clock component is configured to disable the first clock dividing circuit and transmit the signal to the third clock component; wherein, in response to receiving the signal, the third clock component is configured to disable the shortstop circuit and transmit the signal to the fourth clock component; wherein, in response to receiving the signal, the fourth clock component is configured to disable the second clock dividing circuit and transmit the signal to the fifth clock component; wherein, in response to receiving the signal, the fifth clock component is configured to disable the multiplexing circuit and transmit the signal to the sixth clock component; wherein, in response to receiving the signal, the sixth clock component is configured to disable the PLL.
- Claim: 24. The CMU of claim 23 , wherein the PLL controller is configured to output a first clock signal based on an output from the PLL or an oscillator.
- Claim: 25. The CMU of claim 24 , wherein the multiplexing circuit is configured to output one of the first clock signal and a second clock signal.
- Claim: 26. The CMU of claim 25 , wherein the second clock dividing circuit is configured to perform a second dividing operation on an output of the multiplexing circuit to generate a third clock signal.
- Claim: 27. The CMU of claim 26 , wherein the shortstop circuit is configured to selectively stop pulses of the third clock signal to generate a fourth clock signal.
- Claim: 28. The CMU of claim 27 , wherein the first clock dividing circuit is configured to perform a first dividing operation on an output of the shortstop circuit to generate a fifth clock signal.
- Claim: 29. The CMU of claim 28 , wherein the first clock gating circuit is configured to selectively output the fifth clock signal.
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- Primary Examiner: Patel, Nitin G
- Attorney, Agent or Firm: F. Chau & Associates, LLC
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