Einzeltreffer — DigiBib

Disclosed is a CMOS image sensor with global shutters and a method for fabricating the CMOS image sensor. In one embodiment, a semiconductor device, includes: a light-sensing region; a charge-storage region; a light-shielding structure; and at least one via contact; wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein the light-shielding structure is configured over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the signal-processing region, wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, and wherein the light-shielding structure is simultaneously formed with the at least one via contact.

Titel:	Method and apparatus for reducing light leakage at memory nodes in CMOS image sensors
Autor/in / Beteiligte Person:	Taiwan Semiconductor Manufacturing Co., Ltd.
Link:	View record in USPTO Patent Grants (Volltext)
Veröffentlichung:	2023
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Grants Sprachen: English Patent Number: 11791,354 Publication Date: October 17, 2023 Appl. No: 16/870314 Application Filed: May 08, 2020 Assignees: Taiwan Semiconductor Manufacturing Co., Ltd. (Hsin-Chu, TW) Claim: 1. A semiconductor device, comprising: a light-sensing region; a charge-storage region; a transfer gate formed over the charge-storage region; a light-shielding structure; and at least one via contact; wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein the light-shielding structure is configured over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the charge-storage region, wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, wherein the light-shielding structure comprises a first surface and a second surface, wherein the first surface is coplanar with the ILD layer, and the second surface comprises a plurality of wrinkles, wherein each of the plurality of wrinkles comprises a respective lower portion that is higher than an upper portion of the transfer gate, and wherein the light-shielding structure is simultaneously formed with the at least one via contact. Claim: 2. The semiconductor device of claim 1 , wherein the light-shielding structure comprises a first thickness measured between the first surface and a highest point of the second surface, wherein the first thickness is equal to or greater than 150 nanometers. Claim: 3. The semiconductor device of claim 1 , wherein the light-shielding structure comprises tungsten (W) metal and electrically grounded through at least one grounding contact. Claim: 4. The semiconductor device of claim 1 , wherein a second thickness of the ILD layer is at least 330 nanometers. Claim: 5. The semiconductor device of claim 1 , wherein the charge-storage region comprises a charge-storage node. Claim: 6. The semiconductor device of claim 1 , wherein the light-sensing region comprises a complementary metal-oxide-semiconductor (CMOS) photodiode. Claim: 7. The semiconductor device of claim 1 , wherein the at least one via contact is configured to provide electrical contacts to the charge-storage region and is electrically isolated from the light-shielding structure, wherein the at least one via contact comprises W metal. Claim: 8. A Complementary Metal-Oxide-Semiconductor (CMOS) image sensor, comprising: a plurality of pixels configured in a pixel array, wherein each of the plurality of pixels comprises: a light-sensing region; a charge-storage region formed adjacent to the light-sensing region in a lateral direction; a transfer gate formed over the charge-storage region; a light-shielding structure formed over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the charge-storage region, wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, wherein the light-shielding structure comprises a first surface and a second surface, wherein the first surface is coplanar with the ILD layer, and wherein the second surface comprises a plurality of wrinkles, wherein each of the plurality of wrinkles comprises a respective lower portion that is higher than an upper portion of the transfer gate; and at least one via contact that extends through the ILD layer to contact a top surface of the transfer gate. Claim: 9. The CMOS image sensor of claim 8 , wherein each of the plurality of light-shielding structures comprises a first thickness measured between the first surface and a highest point of the second surface, wherein the first thickness is equal to or greater than 150 nanometers. Claim: 10. The CMOS image sensor of claim 8 , wherein the light-shielding structure in each of the plurality of pixels comprises tungsten (W) metal and electrically grounded through at least one grounding contact. Claim: 11. The CMOS image sensor of claim 8 , wherein a second thickness of the ILD layer is at least 330 nanometers. Claim: 12. The CMOS image sensor of claim 8 , wherein the charge-storage region comprises a charge-storage node. Claim: 13. The CMOS image sensor of claim 8 , wherein the at least one via contact is configured to provide electrical contacts to the charge-storage region and is electrically isolated from the light-shielding structure, wherein the at least one via contact comprises W metal. Claim: 14. The CMOS image sensor of claim 8 , further comprising: a vertical shift register (VSR) coupled with the pixel array to perform at least one of the following functions, receiving a row address of the pixel array and driving control lines of the pixel array; a horizontal shift register (HSR) coupled with the pixel array to perform reading output signals from the pixel array; a timing generator coupled to the pixel array, the VSR and the HSR so as to generate a clock signal for synchronization purposes; and a voltage regulator coupled to the pixel array, the VSR and the HSR so as to provide voltage control and maintain voltage levels. Claim: 15. A semiconductor device, comprising: a light-sensing region; a charge-storage region; a transfer gate formed over the charge-storage region; a light-shielding structure; and at least one via contact; wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, and wherein the light-shielding structure is simultaneously formed with the at least one via contact, and wherein the light-shielding structure comprises a first surface and a second surface, the first surface being coplanar with the ILD layer, and the second surface comprises a plurality of wrinkles, wherein each of the plurality of wrinkles comprises a respective lower portion that is higher than an upper portion of the transfer gate. Claim: 16. The semiconductor device of claim 15 , wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein the light-shielding structure is configured over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the charge-storage region. Claim: 17. The semiconductor device of claim 15 , wherein the light-shielding structure comprises tungsten (W) metal and electrically grounded through at least one grounding contact. Claim: 18. The semiconductor device of claim 15 , wherein a first thickness of the light-shielding structure is at least 150 nanometers, and wherein a second thickness of the ILD layer is at least 330 nanometers. Claim: 19. The semiconductor device of claim 15 , wherein the charge-storage region comprises a charge-storage node. Claim: 20. The semiconductor device of claim 15 , wherein the light-sensing region comprises a complementary metal-oxide-semiconductor (CMOS) photodiode. Patent References Cited: 9893104 February 2018 Kobayashi et al. ; 20110242386 October 2011 Machida ; 20120299066 November 2012 Kato ; 20170098676 April 2017 Kobayashi et al. ; 20180213169 July 2018 Onuki ; 20180286905 October 2018 Tsao et al. ; 20190067353 February 2019 Tsao ; 20200105816 April 2020 Chung et al. ; 202015225 April 2020 Primary Examiner: Garces, Nelson Attorney, Agent or Firm: Duane Morris LLP

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Method and apparatus for reducing light leakage at memory nodes in CMOS image sensors