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- Nachgewiesen in: USPTO Patent Grants
- Sprachen: English
- Patent Number: 11803,472
- Publication Date: October 31, 2023
- Appl. No: 17/390274
- Application Filed: July 30, 2021
- Assignees: QUALCOMM Incorporated (San Diego, CA, US)
- Claim: 1. An integrated circuit (IC) configured to operate in two power modes, the IC comprising: a low-power island (LPI) subsystem circuit; and a memory subsystem comprising: a shared memory circuit; a subsystem memory interface configured to, in response to the IC operating in the first power mode: receive a first subsystem memory access request from the LPI subsystem circuit; and access the shared memory circuit in response to the first subsystem memory access request; and an LPI memory interface configured to, in response to the IC operating in the second power mode: receive an LPI memory access request from the LPI subsystem circuit; and access the shared memory circuit in response to the LPI memory access request.
- Claim: 2. The IC of claim 1 , further comprising a plurality of primary subsystem circuits, wherein: the subsystem memory interface is further configured to, in response to the IC operating in the first power mode: receive a second subsystem memory access request from one of the plurality of primary subsystem circuits; and access the shared memory circuit in response to the second subsystem memory access request.
- Claim: 3. The IC of claim 2 , wherein: the LPI subsystem circuit is configured to couple to a first supply voltage source in response to the IC operating in the first power mode and couple to a second supply voltage source in response to the IC operating in the second power mode; the shared memory circuit is configured to: couple to the first supply voltage source in response to the IC operating in the first power mode; and couple to the second supply voltage source in response to the IC operating in the second power mode; and the subsystem memory interface and the plurality of primary subsystems are each further configured to: couple to the first supply voltage source in response to the IC operating in the first power mode; and decouple from the first supply voltage source in response to the IC operating in the second power mode; and the LPI memory interface is further configured to: couple to the second supply voltage source in response to the IC operating in the second power mode; and decouple from the second supply voltage source in response to the IC operating in the first power mode.
- Claim: 4. The IC of claim 2 , wherein: the IC is further configured to couple to an external memory; in response to the IC operating in the first power mode, the subsystem memory interface is further configured to: directly map a memory address in the first subsystem memory access request to a first cache line address in the shared memory circuit; dynamically map a memory address in the second subsystem memory access request to a second cache line address in the shared memory circuit; and access the shared memory circuit on a first memory interface; and in response to the IC operating in the second power mode, the LPI memory interface is further configured to: directly map a memory address in the LPI memory access request to a third cache line in the shared memory circuit; and access the shared memory circuit on a second memory interface.
- Claim: 5. The IC of claim 4 , wherein the subsystem memory interface comprises a tag random-access memory (RAM), the subsystem memory interface further configured to, in response to the IC operating in the first power mode: access the tag RAM to dynamically map the memory address in the second subsystem memory access request to the second cache line address; and provide one of the first cache line address and the second cache line address on the first memory interface.
- Claim: 6. The IC of claim 5 , wherein, in response to the IC operating in the second power mode, the LPI memory interface is further configured to provide the third cache line address on the second memory interface.
- Claim: 7. The IC of claim 6 the memory subsystem further comprising a switch configured to: in response to the IC operating in the first power mode: couple to the first supply voltage source; and couple the subsystem memory interface to the first memory interface of the shared memory circuit; and in response to the IC operating in the second power mode: couple to the second supply voltage source; and couple the LPI memory interface to the second memory interface of the shared memory circuit.
- Claim: 8. The IC of claim 4 , wherein the LPI subsystem circuit comprises an LPI processor configured to: generate the first subsystem memory access request to access data stored in the external memory in response to the IC operating in the first power mode; and generate the LPI memory access request to access data stored in the shared memory circuit in response to the IC operating in the second power mode.
- Claim: 9. The IC of claim 8 , wherein the LPI subsystem circuit is further configured to: generate, in response to the IC operating in the first power mode, the first subsystem memory access request on a first LPI interface coupled to the subsystem memory interface; and generate, in response to the IC operating in the second power mode, the LPI memory access request on a second LPI interface coupled to the LPI memory interface.
- Claim: 10. The IC of claim 9 , wherein the LPI subsystem circuit further comprises: a tightly-coupled memory (TCM) configured to store a first data; and an LPI cache circuit, wherein: the shared memory circuit is configured to store a second data; and in response to the IC operating in the second power mode, the LPI cache circuit is configured to store at least one of a version of the first data and a version of the second data.
- Claim: 11. The IC of claim 1 , wherein: a plurality of subsystem circuits comprises at least one of a central processing unit (CPU), a graphics processing unit (GPU), a peripheral interface, and a modem; at least one of the plurality of subsystem circuits comprises an internal cache memory configured to store a first version of a subsystem data stored in an external memory; and in response to the IC operating in the first power mode, the shared memory circuit is configured to store a second version of the subsystem data stored in the external memory.
- Claim: 12. A method of operating an integrated circuit (IC) in two power modes, the method comprising: in response to the IC operating in the first power mode: receiving, in a subsystem memory interface in a memory subsystem, a first subsystem memory access request from a low-power island (LPI) subsystem circuit; and accessing, by the subsystem memory interface, a shared memory circuit in response to the first subsystem memory access request; and in response to the IC operating in the second power mode: receiving, in an LPI memory interface in the memory subsystem, an LPI memory access request from the LPI memory interface; and accessing, by the LPI memory interface, the shared memory circuit in response to the LPI memory access request.
- Claim: 13. The method of claim 12 , further comprising: receiving, in the subsystem memory interface in the memory subsystem, a second subsystem memory access request from one of a plurality of primary subsystem circuits; and accessing, by the subsystem memory interface, the shared memory circuit in response to the second subsystem memory access request.
- Claim: 14. The method of claim 13 , further comprising: in response to the IC operating in the first power mode: coupling the LPI subsystem circuit, the shared memory circuit, the subsystem memory interface, and the plurality of primary subsystem circuits to a first supply voltage source; and decoupling the LPI memory interface from a second supply voltage source; and in response to the IC operating in the second power mode: coupling the LPI subsystem circuit, the shared memory circuit, and the LPI memory interface to the second supply voltage source; and decoupling the subsystem memory interface and the plurality of primary subsystem circuits from the first supply voltage source.
- Claim: 15. The method of claim 13 , further comprising: dynamically mapping a memory address in the second subsystem memory access request to a first cache line address in the shared memory circuit; accessing, by the subsystem memory interface, the first cache line in the shared memory circuit on a first memory interface; directly mapping a memory address in the first subsystem memory request to a second cache line address in the shared memory circuit; and accessing, by the LPI memory interface, the second cache line address on a second memory interface.
- Claim: 16. The method of claim 15 , further comprising, in response to the IC operating in the first power mode: receiving, in the subsystem memory interface in the memory subsystem, a third subsystem memory access request from the LPI subsystem circuit; and accessing, by the subsystem memory interface, a cache line in the shared memory circuit on the first memory interface, the cache line comprising a cache line address directly mapped to the memory address in the third subsystem memory access request.
- Claim: 17. The method of claim 16 , the dynamic mapping further comprising: determining, by accessing a tag random-access memory (RAM), a cache line address of the first cache line in the shared memory circuit corresponding to the memory address; and providing the cache line address of the first cache line on the first memory interface.
- Claim: 18. The method of claim 17 , further comprising, in response to the IC operating in the second power mode, providing by the LPI memory interface, a cache line address of the second cache line to the second memory interface.
- Claim: 19. The method of claim 18 , further comprising: in response to the IC operating in the first power mode, coupling, by a switch, the first memory interface to the shared memory circuit; and in response to the IC operating in the second power mode, coupling, by the switch, the second memory interface to the shared memory circuit.
- Claim: 20. The method of claim 12 , further comprising: generating, by an LPI processor in the LPI subsystem circuit, the first subsystem memory access request in response to the IC operating in the first power mode; and generating, by the LPI processor in the LPI subsystem circuit, the LPI memory access request in response to the IC operating in the second power mode.
- Claim: 21. The method of claim 20 , further comprises: generating, in response to the IC operating in the first power mode, the first subsystem memory access request on a first LPI memory interface coupled to the subsystem memory interface; and generating, in response to the IC operating in the second power mode, the LPI memory access request on a second LPI memory interface coupled to the LPI memory interface.
- Claim: 22. The method of claim 21 , further comprising, in response to the IC operating in the second power mode: storing a first LPI data for the LPI subsystem circuit in a tightly-coupled memory (TCM); storing a second LPI data in the shared memory circuit; and storing, in an LPI cache circuit, at least one of a version of the first LPI data and a version of the second LPI data.
- Claim: 23. The method of claim 22 , wherein: storing, in a cache memory of one of the plurality of primary subsystem circuits, a first version of a subsystem data stored in an external memory; and in response to the IC operating in the first power mode, storing a second version of the subsystem data in the shared memory circuit.
- Patent References Cited: 9335809 May 2016 Younger ; 20140297959 October 2014 Shiu et al. ; 20160019936 January 2016 Partiwala et al. ; 20170090539 March 2017 Tiwari et al. ; 20190129493 May 2019 Li ; 20200103956 April 2020 Srinivas et al. ; 20210064113 March 2021 Laurent
- Other References: International Search Report and Written Opinion for International Patent Application No. PCT/US2022/073007, dated Oct. 5, 2022, 14 pages. cited by applicant
- Primary Examiner: Farrokh, Hashem
- Attorney, Agent or Firm: W&T/Qualcomm
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