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- Nachgewiesen in: USPTO Patent Grants
- Sprachen: English
- Patent Number: 11837,542
- Publication Date: December 05, 2023
- Appl. No: 17/583078
- Application Filed: January 24, 2022
- Assignees: Intel Corporation (Santa Clara, CA, US)
- Claim: 1. An integrated circuit structure, comprising: a conductive interconnect over a dielectric layer, the conductive interconnect having a bottom and sidewalls, and the dielectric layer having an uppermost surface; and a liner material along the bottom and along lower portions of the sidewalls of the conductive interconnect, the liner material forming a liner layer, and wherein the liner layer is not along upper portions of the sidewalls of the conductive interconnect, and wherein the liner layer has an uppermost surface above the uppermost surface of the dielectric layer.
- Claim: 2. The integrated circuit structure of claim 1 , wherein the bottom surface of the conductive interconnect is below an uppermost surface of the dielectric layer.
- Claim: 3. The integrated circuit structure of claim 1 , further comprising: an air gap laterally adjacent to the conductive interconnect, the air gap over the dielectric layer.
- Claim: 4. The integrated circuit structure of claim 1 , further comprising: a second dielectric layer laterally adjacent to the conductive interconnect, the second dielectric layer over the dielectric layer.
- Claim: 5. The integrated circuit structure of claim 1 , wherein each upper portion of a corresponding sidewall of the conductive interconnect has a length greater than a corresponding lower portion of the corresponding sidewall of the conductive interconnect.
- Claim: 6. The integrated circuit structure of claim 1 , wherein each upper portion of a corresponding sidewall of the interconnect is about 80% of an entirety of the corresponding sidewall of the conductive interconnect.
- Claim: 7. The integrated circuit structure of claim 1 , wherein the conductive interconnect comprises a metal selected from the group consisting of copper, cobalt, ruthenium, and aluminum.
- Claim: 8. The integrated circuit structure of claim 1 , wherein the liner material comprises a material selected from the group consisting of titanium nitride, titanium, ruthenium, tantalum nitride, and molybdenum nitride.
- Claim: 9. The integrated circuit structure of claim 1 , further comprising: a hermetic liner laterally adjacent to an upper portion of the liner layer.
- Claim: 10. The integrated circuit structure of claim 9 , wherein the hermetic liner comprises a material selected from the group consisting of hafnium oxide, aluminum oxide, and carbon-doped silicon nitride.
- Claim: 11. A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a conductive interconnect over a dielectric layer, the conductive interconnect having a bottom and sidewalls, and the dielectric layer having an uppermost surface; and a liner material along the bottom and along lower portions of the sidewalls of the conductive interconnect, the liner material forming a liner layer, and wherein the liner layer is not along upper portions of the sidewalls of the conductive interconnect, and wherein the liner layer has an uppermost surface above the uppermost surface of the dielectric layer.
- Claim: 12. The computing device of claim 11 , further comprising: a memory coupled to the board.
- Claim: 13. The computing device of claim 11 , further comprising: a communication chip coupled to the board.
- Claim: 14. The computing device of claim 11 , further comprising: a display coupled to the board.
- Claim: 15. The computing device of claim 11 , further comprising: a GPS coupled to the board.
- Claim: 16. The computing device of claim 11 , further comprising: a battery coupled to the board.
- Claim: 17. The computing device of claim 11 , further comprising: a camera coupled to the board.
- Claim: 18. The computing device of claim 11 , further comprising: a speaker coupled to the board.
- Claim: 19. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
- Claim: 20. The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
- Claim: 21. An integrated circuit structure, comprising: a conductive interconnect over a dielectric layer, the conductive interconnect having a bottom and sidewalls; a liner material along the bottom and along lower portions of the sidewalls of the conductive interconnect, the liner material forming a liner layer, and wherein the liner layer is not along upper portions of the sidewalls of the conductive interconnect; and an air gap laterally adjacent to the conductive interconnect, the air gap over the dielectric layer.
- Claim: 22. An integrated circuit structure, comprising: a conductive interconnect over a dielectric layer, the conductive interconnect having a bottom and sidewalls; a liner material along the bottom and along lower portions of the sidewalls of the conductive interconnect, the liner material forming a liner layer, and wherein the liner layer is not along upper portions of the sidewalls of the conductive interconnect, and wherein each upper portion of a corresponding sidewall of the conductive interconnect has a length greater than a corresponding lower portion of the corresponding sidewall of the conductive interconnect.
- Claim: 23. The integrated circuit structure of claim 22 , wherein each upper portion of the corresponding sidewall of the interconnect is about 80% of an entirety of the corresponding sidewall of the conductive interconnect.
- Claim: 24. An integrated circuit structure, comprising: a conductive interconnect over a dielectric layer, the conductive interconnect having a bottom and sidewalls; a liner material along the bottom and along lower portions of the sidewalls of the conductive interconnect, the liner material forming a liner layer, and wherein the liner layer is not along upper portions of the sidewalls of the conductive interconnect; and a hermetic liner laterally adjacent to an upper portion of the liner layer.
- Claim: 25. The integrated circuit structure of claim 24 , wherein the hermetic liner comprises a material selected from the group consisting of hafnium oxide, aluminum oxide, and carbon-doped silicon nitride.
- Patent References Cited: 7488679 February 2009 Standaert ; 9455403 September 2016 Lai et al. ; 20120074571 March 2012 Lavoie ; 20140264864 September 2014 Weng et al. ; 20160035675 February 2016 Hegde ; 20160163587 June 2016 Backes ; 20160197013 July 2016 Backes et al. ; 3034655 June 2016 ; 1020160014558 February 2016
- Other References: International Search Report and Written Opinion for PCT/US2017/054018 dated Jun. 21, 2018, 13 pages. cited by applicant ; International Preliminary Report on Patentability for International Patent Application No. PCT/US2017/054018, dated Apr. 9, 2020, 8 pgs. cited by applicant
- Assistant Examiner: Booker, Vicki B.
- Primary Examiner: Ahmed, Shahed
- Attorney, Agent or Firm: Schwabe, Williamson & Wyatt, P.C.
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