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An integrated circuit (IC) device comprises a high voltage semiconductor device (HVSD) on a frontside of a semiconductor body and further comprises an electrode on a backside of the semiconductor body opposite the frontside. The HVSD may, for example, be a transistor or some other suitable type of semiconductor device. The electrode has one or more gaps directly beneath the HVSD. The one or more gaps enhance the effectiveness of the electrode for improving the breakdown voltage of the HVSD.

Titel:	High voltage device with boosted breakdown voltage
Autor/in / Beteiligte Person:	Taiwan Semiconductor Manufacturing Company, Ltd.
Link:	View record in USPTO Patent Grants (Volltext)
Veröffentlichung:	2024
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Grants Sprachen: English Patent Number: 11935,918 Publication Date: March 19, 2024 Appl. No: 17/572945 Application Filed: January 11, 2022 Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. (Hsinchu, TW) Claim: 1. A method, comprising: forming a high voltage semiconductor device (HVSD) on a front side of a semiconductor body; and forming an insulating layer and a conductive layer on a backside of the semiconductor body, wherein the insulating layer is between the conductive layer and the semiconductor body; and etching the conductive layer to define a contiguous electrode directly beneath the HVSD and an opening in the contiguous electrode; wherein the opening is directly beneath the HVSD. Claim: 2. The method of claim 1 , further comprising: forming a metal interconnect structure on the front side of the semiconductor body; forming a through-substrate via; and connecting the contiguous electrode to the metal interconnect structure through the through-substrate via. Claim: 3. The method of claim 1 , further comprising biasing the contiguous electrode to increase a breakdown voltage of the HVSD. Claim: 4. The method of claim 3 , wherein the increase in the breakdown voltage is enhanced by the opening. Claim: 5. The method of claim 1 , wherein the contiguous electrode has two or more openings directly beneath the HVSD. Claim: 6. The method of claim 1 , wherein the opening is a cut-out within the contiguous electrode. Claim: 7. A method, comprising: providing a semiconductor body having a first side and a second side, wherein the second side is opposite the first side across a thickness of the semiconductor body; forming a high voltage semiconductor device on the first side of the semiconductor body; forming a contiguous electrode on or in a dielectric layer on the second side of the semiconductor body, wherein the contiguous electrode is insulated from the semiconductor body by the dielectric layer, the contiguous electrode is directly opposite the high voltage semiconductor device, and the contiguous electrode has sidewalls that define a gap that is directly opposite the high voltage semiconductor device; a first portion of the contiguous electrode is on a first side of the gap; and a second portion of the contiguous electrode is on a second side of the gap, opposite the first side of the gap. Claim: 8. The method of claim 7 , wherein the gap is longer than the high voltage semiconductor device. Claim: 9. The method of claim 7 , wherein an area of the contiguous electrode directly underneath the high voltage semiconductor device is greater than an area of the gap directly underneath the high voltage semiconductor device. Claim: 10. The method of claim 7 , wherein the gap has a shape that corresponds to a shape of a source region, a drain region, a gate electrode, or a channel that is part of the high voltage semiconductor device and is on the first side. Claim: 11. The method of claim 7 , wherein: the high voltage semiconductor device has a source region and a drain region that are elongated in a transverse direction to a source-to-drain direction; and the gap is elongated in the transverse direction. Claim: 12. The method of claim 7 , wherein the high voltage semiconductor device is a lateral doubly diffused metal oxide semiconductor (LDMOS) device. Claim: 13. The method of claim 7 , wherein the high voltage semiconductor device is a transistor, and the gap increases a breakdown voltage of the transistor. Claim: 14. The method of claim 7 , further comprising forming a deep trench isolation structure, wherein the deep trench isolation structure surrounds the high voltage semiconductor device and extends from the first side and a second side. Claim: 15. The method of claim 7 , wherein the contiguous electrode surrounds the gap. Claim: 16. A method, comprising: forming a plurality of high voltage semiconductor devices on a first side of a semiconductor body, wherein the high voltage semiconductor devices have footprints; and forming a plurality of contiguous electrodes on a second side of the semiconductor body, wherein the contiguous electrodes extend over some but not all of the footprints of corresponding high voltage semiconductor devices in a pattern that is repeated for each of the plurality of high voltage semiconductor devices; wherein a dielectric layer separates the plurality of contiguous electrodes from the semiconductor body; and each of the plurality of contiguous electrodes has internal sidewalls. Claim: 17. The method of claim 16 , wherein the internal sidewalls define a gap surrounded by a one of the plurality of contiguous electrodes. Claim: 18. The method of claim 16 , wherein: each of the plurality of high voltage semiconductor devices is surrounded by a distinct deep trench isolation structure; and each of the plurality of contiguous electrodes is entirely within an outer perimeter of one of the deep trench isolation structures. Claim: 19. The method of claim 16 , wherein each of the plurality of contiguous electrodes has a pair of the internal sidewalls separated by a dielectric within the respective footprint. Claim: 20. The method of claim 16 , wherein each of the plurality of contiguous electrodes is longer than a respective one of the plurality of high voltage semiconductor devices. Patent References Cited: 9761525 September 2017 Hook ; 20190109232 April 2019 Goktepeli et al. ; 20190393340 December 2019 Liang ; 20200259016 August 2020 Mori Primary Examiner: Gupta, Raj R Attorney, Agent or Firm: Eschweiler & Potashnik, LLC

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High voltage device with boosted breakdown voltage