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- Nachgewiesen in: USPTO Patent Grants
- Sprachen: English
- Patent Number: 12002,747
- Publication Date: June 04, 2024
- Appl. No: 17/680489
- Application Filed: February 25, 2022
- Assignees: Intel Corporation (Santa Clara, CA, US)
- Claim: 1. An apparatus, comprising: a semiconductor package substrate; first and second semiconductor dies on a first side of the semiconductor package substrate; and a bridge interconnect between the first side and a second side of the semiconductor package substrate, the second side opposite the first side, the bridge interconnect comprising: a first section coupling the first semiconductor die to the second semiconductor die; and a second section between the first semiconductor die and the second side, the second section comprising ground and power planes coupled to the first semiconductor die.
- Claim: 2. The apparatus of claim 1 , wherein the ground and power planes are coupled to package connections on the second side.
- Claim: 3. The apparatus of claim 1 , further comprising a passive component coupled to the ground and power planes.
- Claim: 4. The apparatus of claim 3 , wherein the passive component is embedded in the bridge interconnect.
- Claim: 5. The apparatus of claim 3 , wherein the passive component resides on an external surface of the semiconductor package substrate.
- Claim: 6. The apparatus of claim 1 , wherein: the ground plane is a first ground plane; the power plane is a first power plane; the first section comprises electrical signal routing and second ground and second power planes, the electrical signal routing is between the second ground and second power planes and couples the first semiconductor die to the second semiconductor dies; and the second ground and second power planes are coupled to the first ground and first power planes.
- Claim: 7. The apparatus of claim 1 , further comprising a third semiconductor die on the first side of the semiconductor package substrate, and a third section of the bridge interconnect, wherein the first semiconductor die is between the second and third semiconductor dies, and the third section couples the first semiconductor die to the third semiconductor die.
- Claim: 8. The apparatus of claim 7 , wherein: the ground plane is a first ground plane; the power plane is a first power plane; the first section comprises first electrical signal routing and second ground and second power planes; the first electrical signal routing is between the second ground and second power planes and couples the first semiconductor die to the second semiconductor die; the second ground and second power planes are coupled to the first ground and first power planes; the third section comprises second electrical signal routing third ground and third power planes; the second electrical signal routing is between the third ground and third power planes and couples the first semiconductor die to the third semiconductor die; and the third ground and third power planes are coupled to the first ground and first power planes.
- Claim: 9. The apparatus of claim 1 , wherein: the ground plane is a first ground plane; the power plane is a first power plane; and the bridge interconnect further comprises a fourth section comprising second ground and second power planes that couple the second semiconductor die to the first ground and first power planes.
- Claim: 10. The apparatus of claim 9 , wherein the fourth section is adjacent the first section.
- Claim: 11. The apparatus of claim 1 , wherein the bridge interconnect comprises a lateral cross section at least partially spanning under the first semiconductor die and the second semiconductor die.
- Claim: 12. An apparatus comprising: a package substrate; first and second dies on the package substrate; and a bridge component coupling the first and second dies, the bridge component comprising ground and power planes between and coupling the first die and package connections opposite the first die.
- Claim: 13. The apparatus of claim 12 , wherein the bridge component is embedded between opposing first and second surfaces of the package substrate, the first and second dies are on the first surface, and the package connections are on the second surface.
- Claim: 14. The apparatus of claim 12 , wherein the ground plane is a first ground plane, and the power plane is a first power plane, and further comprising second ground and second power planes, wherein the second die is coupled to the first ground and first power planes by the second ground and second power planes.
- Claim: 15. The apparatus of claim 12 , wherein the ground plane is a first ground plane, and the power plane is a first power plane, and further comprising second ground and second power planes, wherein the second ground plane is coupled to the first ground plane, the second power plane is coupled to the first power plane, and the second ground and second power planes are between the first die and the bridge component.
- Claim: 16. The apparatus of claim 12 , wherein the ground plane is a first ground plane, and the power plane is a first power plane, and further comprising second ground and second power planes, wherein the second ground plane is coupled to the first ground plane, the second power plane is coupled to the first power plane, and the second ground and second power planes are on or coupled to a surface of the bridge component opposite the first die.
- Claim: 17. The apparatus of claim 16 , wherein the second ground and second power planes couple the first ground and first power planes to the package connections.
- Claim: 18. The apparatus of claim 12 , further comprising a capacitor coupled to the first ground and power planes.
- Claim: 19. The apparatus of claim 18 , wherein the capacitor is between the first die and the first ground and power planes.
- Claim: 20. The apparatus of claim 12 , further comprising a third die on the package substrate, wherein the first die is between the second and third dies, and the bridge component couples the first and third dies.
- Patent References Cited: 10535608 January 2020 Rubin et al. ; 20170330835 November 2017 Deshpande ; 20190043792 February 2019 Weerasekera ; 20190295952 September 2019 Sikka ; 20210020574 January 2021 Yu ; 20210134724 May 2021 Rubin ; 20210159211 May 2021 Rubin ; 20210193567 June 2021 Cheah et al.
- Other References: U.S. Appl. No. 17/025,115, filed Sep. 18, 2020, Integrated Bridge for Die-to-Die Interconnects. cited by applicant ; “U.S. Appl. No. 17/025,115, 312 Amendment filed Feb. 17, 2022”, 3 pgs. cited by applicant ; “U.S. Appl. No. 17/025,115, Notice of Allowance dated Nov. 17, 2021”, 18 pgs. cited by applicant ; “U.S. Appl. No. 17/025,115, Response filed Sep. 3, 2021 to Restriction Requirement dated Jul. 8, 2021”, 6 pgs. cited by applicant ; “U.S. Appl. No. 17/025,115, Restriction Requirement dated Jul. 8, 2021”, 8 pgs. cited by applicant ; “Malaysian Application Serial No. PI2019007653, Substantive Examination Adverse Report dated Oct. 6, 2022”, 4 pgs. cited by applicant ; Notice of Allowance from Malaysian Patent Application No. PI2019007653 notified Jan. 30, 2024, 1 pg. cited by applicant ; Office Action from Taiwanese Patent Application No. 109133525 notified Jan. 11, 2024, 6 pgs. cited by applicant
- Primary Examiner: Mojaddedi, Omar F
- Attorney, Agent or Firm: Essential Patents Group, LLP
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