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- Nachgewiesen in: USPTO Patent Grants
- Sprachen: English
- Patent Number: 12015,412
- Publication Date: June 18, 2024
- Appl. No: 18/060857
- Application Filed: December 01, 2022
- Assignees: ADVANCED MICRO DEVICES, INC. (Santa Clara, CA, US)
- Claim: 1. A semiconductor package for skew matching in a die-to-die interface, comprising: a first die including a first plurality of connection points and a phase locked loop, the phase locked loop configured to output a local clock signal and to output a strobe signal having a phase offset relative to the local clock signal, the local clock signal routed to a first transmit block of the first die and the strobe signal routed to the first transmit block of the first die; a second die comprising a second plurality of connection points; and a plurality of connection paths of a substantially same length, wherein each connection path couples a connection point of the first plurality of connection points to a corresponding connection point of the second plurality of connection points, the plurality of connection paths including a data subset of the connection paths for transmitting data signals from the first die to the second die based on the local clock signal and including a strobe subset of the connection paths for transmitting the strobe signal from the first die to the second die.
- Claim: 2. The semiconductor package of claim 1 , wherein the phase offset is ninety degrees.
- Claim: 3. The semiconductor package of claim 1 , wherein the second die is aligned with the first die and each connection point of the first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of the second plurality of connection points of the second die.
- Claim: 4. The semiconductor package of claim 1 , wherein a difference between a strobe delay and a data delay is less than a threshold, the strobe delay resulting from transmitting the strobe signal from the first die to the second die via the strobe subset of the connection paths, and the data delay resulting from transmitting the data signals from the first die to the second die via the data subset of the connection paths.
- Claim: 5. The semiconductor package of claim 4 , wherein the strobe delay is a combination of a delay from routing the strobe signal from the phase locked loop to the first transmit block of the first die, a delay from transmitting the strobe signal from the first die to the second die via the strobe subset of the connection paths, and a delay from routing the strobe signal from connection points of the second plurality of connection points coupled to the strobe subset of the connection paths to a second receive block of the second die.
- Claim: 6. The semiconductor package of claim 5 , wherein the data delay is a combination of a delay from routing the local clock from the phase locked loop to the transmit block of the first die, a delay from transmitting a data signal from the first die to the second die via the data subset of the connection paths, and a delay from routing the data signal from connection points of the second plurality of connection points coupled to the data subset of the connection paths to the receive block of the second die.
- Claim: 7. The semiconductor package of claim 1 , wherein the first transmit block of the first die is linearly aligned with a second receive block of the second die and a second transmit block of the second die is linearly aligned with a first receive block of the first die.
- Claim: 8. The semiconductor package of claim 1 , wherein the first transmit block is configured to transmit the strobe signal to a second receive block of second die via the strobe subset of the connection paths and the first transmit block is configured to transmit data signals to the receive block of the second die via the data subset of the connection paths.
- Claim: 9. The semiconductor package of claim 1 , further comprising a clock coupled to the first die and the second die, the phase locked loop of the first die generating the local clock using a signal from the clock as a reference.
- Claim: 10. The semiconductor package of claim 1 , wherein the first die further comprises: a strobe interpolator having an input coupled to the phase locked loop and an output coupled to the first transmit block, the strobe interpolator configured to adjust a phase of the strobe signal.
- Claim: 11. The semiconductor package of claim 10 , wherein the first die further comprises: a clock interpolator having a clock input coupled to the phase locked loop and a clock output coupled to the first transmit block, the clock interpolator configured to adjust a phase of the local clock signal.
- Claim: 12. A method for transmitting data using a die-to-die interface, the method comprising: generating a local clock signal at a first die; generating a strobe signal at the first die, the strobe signal having a phase offset from the local clock signal; transmitting the strobe signal from the first die to a second die via a strobe subset of connection paths; and transmitting, based on the local clock signal, data signals from the first die to the second die via a data subset of connection paths, wherein: the first die comprises a first plurality of connection points; the second die comprises a second plurality of connection points; and each connection point of the first plurality of connection points is coupled to a corresponding connection point of the second plurality of connection points through a connection path, each connection path comprising a substantially same length, and is included in one of: the data subset of connection paths for transmitting data from the first die to the second die based on the local clock signal and the strobe subset of connection paths for transmitting the strobe signal from the first die to the second die.
- Claim: 13. The method of claim 12 , wherein each connection point of the first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of the second plurality of connection points of the second die.
- Claim: 14. The method of claim 12 , wherein a first transmit block of the first die is linearly aligned with a second receive block of the second die and a first transmit block of the second die is linearly aligned with a second receive block of the first die.
- Claim: 15. The method of claim 12 , wherein a strobe delay from transmitting the strobe signal from the first die to the second die via the strobe subset of the connection paths is within a threshold amount of a data delay from transmitting the data signals from the first die to the second die via the data subset of the connection paths.
- Claim: 16. The method of claim 15 , wherein the strobe delay is a combination of a delay from routing the strobe signal from a local clock generation circuit of the first die to a first transmit block of the first die, a delay from transmitting the strobe signal from the first die to the second die via the strobe subset of the connection paths, and a delay from routing the strobe signal from connection points of the second plurality of connection points coupled to the strobe subset of the connection paths to a second receive block of the second die.
- Claim: 17. The method of claim 16 , wherein the data delay is a combination of a delay from routing the local clock from a local clock generation circuit of the first die to the first transmit block of the first die, a delay from transmitting a data signal from the first die to the second die via the data subset of the connection paths, and a delay from routing the data signal from connection points of the second plurality of connection points coupled to the data subset of the connection paths to the second receive block of the second die.
- Claim: 18. The method of claim 12 , wherein generating the local clock signal at the first die comprises: receiving a clock signal at a local clock generation circuit included in the first die; and generating the local clock signal using the clock signal as a reference for the local clock generation circuit.
- Claim: 19. A semiconductor die comprising: a phase locked loop and a transmit block, the transmit block comprising a first plurality of connection points, and a first plurality of connection segments, wherein: the phase locked loop is configured to output a local clock signal and to output a strobe signal having a phase offset relative to the local clock signal; the local clock signal and the first strobe signal are routed to the first transmit block; and each of the first connection segments is coupled to one of the first plurality of connection points and is further configured to form a connection path by coupling to one of a second plurality of connection segments of a second die, each of the second plurality of connection segments coupled to one of a second plurality of connection points of the second die, wherein each connection path has a substantially same length.
- Claim: 20. The semiconductor die of claim 19 , wherein each of the first plurality of connection points is configured to be substantially equidistant to a corresponding one of the second plurality of connection points of the second die when the second die is aligned with the first die.
- Patent References Cited: 9245870 January 2016 Peterson ; 10424921 September 2019 Dubowski ; 11574670 February 2023 Moon ; 11693808 July 2023 Noguera Serra ; 20070232091 October 2007 Hong ; 20130318266 November 2013 Thomas ; 20160034417 February 2016 Chavez et al. ; 20160147708 May 2016 Freudenberger et al. ; 20160170934 June 2016 Haejong ; 20170063353 March 2017 Coteus ; 20220206608 June 2022 Shin ; 20230195678 June 2023 Jayaraman ; 2016060780 April 2016
- Other References: 1 International Search Report and Written Opinion, PCT/US2022/052736, dated Mar. 27, 2023, 8 pages. cited by applicant
- Primary Examiner: Jager, Ryan
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