True random number generator implemented in 130 nm CMOS nanotechnology
In: MONTEIRO, Pedro; OLIVEIRA, Luís; CASALEIRO, João – True random number generator implemented in 130 nm CMOS nanotechnology. In 2022 International Young Engineers Forum (YEF-ECE). Caparica, Lisbon, Portugal: IEEE, 2022. ISBN 978-1-6654-6731-5. Pp. 52-56.; 978-1-6654-6731-5; (2022-08-11) S. 52-56
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Zugriff:
Random generators systems have the capacity to generate cryptographic keys which, when mixed with the in formation, hide it in an efficient and timely manner. There are two categories of RNG, being truly random (TRNG) or pseudorandom (PRNG). To study the entropy source based on the noise of an oscillator, and to achieve that, an RNG circuit was designed to have a low power consumption, a high randomness and a low cost and area usage. The chosen architecture for this paper is a hybrid RNG, which uses oscillators and a chaotic circuit to generate the random bits. With the simulation of the circuit, it was found to be at the objectives mark, having a low power consumption of 1.19 mW, a high throughput of 25 Mbit/s and an energy per bit of 47.6 pJ/bit. However, due to limitations with the simulation, it wasn’t possible to run all the statistical tests, although all the ran tests were passed.
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True random number generator implemented in 130 nm CMOS nanotechnology
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| Autor/in / Beteiligte Person: | Monteiro, Pedro ; Oliveira, Luís ; Casaleiro, João ; RCIPL |
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| Quelle: | MONTEIRO, Pedro; OLIVEIRA, Luís; CASALEIRO, João – True random number generator implemented in 130 nm CMOS nanotechnology. In 2022 International Young Engineers Forum (YEF-ECE). Caparica, Lisbon, Portugal: IEEE, 2022. ISBN 978-1-6654-6731-5. Pp. 52-56.; 978-1-6654-6731-5; (2022-08-11) S. 52-56 |
| Veröffentlichung: | IEEE, 2022 |
| Medientyp: | unknown |
| DOI: | 10.1109/YEF-ECE55092.2022.9849994 |
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