High-gain monolithic 3D CMOS inverter using layered semiconductors
In: Applied Physics Letters, Jg. 111 (2017-11-27), Heft 22
Online
academicJournal
- 222101 - 222101
We experimentally demonstrate a monolithic 3D integrated complementary metal oxide semiconductor (CMOS) inverter using layered transition metal dichalcogenide semiconductor N-channel (NMOS) and P-channel (PMOS) MOSFETs, which are sequentially integrated on two levels. The two devices share a common gate. Molybdenum disulphide and tungsten diselenide are used as channel materials for NMOS and PMOS, respectively, with an ON-to-OFF current ratio (ION/IOFF) greater than 106 and electron and hole mobilities of 37 and 236 cm2/Vs, respectively. The voltage gain of the monolithic 3D inverter is about 45 V/V at a supply voltage of 1.5 V and a gate length of 1 μm. This is the highest reported gain at the smallest gate length and the lowest supply voltage for any 3D integrated CMOS inverter using any layered semiconductor.
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High-gain monolithic 3D CMOS inverter using layered semiconductors
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Autor/in / Beteiligte Person: | Sachid, AB ; Desai, SB ; Javey, A ; Hu, C |
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Zeitschrift: | Applied Physics Letters, Jg. 111 (2017-11-27), Heft 22 |
Veröffentlichung: | eScholarship, University of California, 2017 |
Medientyp: | academicJournal |
Umfang: | 222101 - 222101 |
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