Design of a comparator in CMOS SOI
In: Proc. 4th IEEE Int. Workshop on System-on-Chip for Real-Time Applications, IWSOC'04, 2004, S. 229-232
Online
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Zugriff:
This paper gives an introduction to the silicon-on-insulator (SOI) CMOS technology and presents the major advantages and disadvantages of using SOI. It also presents the design of a comparator, which has been sent for manufacturing, designed in a 0.13 μm partially depleted SOI CMOS process. The comparator is a first step towards the design of a complete 6-bit flash analog-to-digital converter, with a sampling frequency of 1.5 GHz.
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Design of a comparator in CMOS SOI
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Autor/in / Beteiligte Person: | Säll, Erik ; Vesterbacka, Mark |
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Zeitschrift: | Proc. 4th IEEE Int. Workshop on System-on-Chip for Real-Time Applications, IWSOC'04, 2004, S. 229-232 |
Veröffentlichung: | 2004 |
Medientyp: | unknown |
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