Growth of SiGe layers in source and drain regions for 10 nm node complementary metal-oxide semiconductor (CMOS)

In this study, the integration of Si 1−x Ge x (50% ≤ x ≤ 60%) selective epitaxy on source/drain regions in 10 nm node FinFET has been presented. One of the major process issues was the sensitivity of Si-fins’ shape to ex- and in-situ cleaning prior to epitaxy. For example, the sharpness of Si-fins could easily be damaged during the wafer washing. The results showed that a DHF dip before the normal cleaning, was essential to clean the Si-fins while in-situ annealing in range of 780–800 °C was needed to remove the native oxide for high epitaxial quality. Because of smallness of fins, the induced strain by SiGe could not be directly measured by X-ray beam in a typical XRD tool in the lab or even in a Synchrotron facility. Further analysis using nano-beam diffraction technique in high-resolution transmission electron microscope also failed to provide information about strain in the FinFET structure. Therefore, the induced strain by SiGe was simulated by technology computer-aided design program and the Ge content was measured by using energy dispersive spectroscopy. Simulation results showed 0.8, 1 and 1.3 GPa for Ge content of 40%, 50% and 60%, respectively. A kinetic gas model was also introduced to predict the SiGe profile on Si-fins with sharp triangular shape. The input parameters in the model includes growth temperature, partial pressure of the reactant gases and the exposed Si coverage in the chip area.