A 0.13µm CMOS ΔΣ PLL FM Transmitter
In: 29th Norchip conference, 2011,Lund, Sweden,-- [Host publication title missing] ELLIIT: the Linköping-Lund initiative on IT and mobile communication, 2011
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Zugriff:
A short range FM transmitter is presented. It uses an architecture where the output frequency of a phase locked loop (PLL) is modulated by varying the division number of the feedback divider, using the 1-bit output of a ΔΣ ADC. The measured total harmonic distortion (THD) plus noise is less than 1% at 75 kHz deviation. The transmitter is fully integrated in a 0.13µm CMOS process and the core area is 0.24 mm2. The current consumption is 4.4mA from a 1.2V supply.
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A 0.13µm CMOS ΔΣ PLL FM Transmitter
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| Autor/in / Beteiligte Person: | Wu, Ying ; Liu, Xiaodong ; Ye, Dawei ; Viswam, Vijay ; Zhu, Lin ; Lu, Ping ; Radjen, Dejan ; Sjöland, Henrik |
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| Zeitschrift: | 29th Norchip conference, 2011,Lund, Sweden,-- [Host publication title missing] ELLIIT: the Linköping-Lund initiative on IT and mobile communication, 2011 |
| Veröffentlichung: | 2011 |
| Medientyp: | unknown |
| DOI: | 10.1109/NORCHP.2011.6126744 |
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