Theory and Design of a CT Delta Sigma Modulator with Low Sensitivity to Loop-Delay Variations
In: Analog Integrated Circuits and Signal Processing ELLIIT: the Linköping-Lund initiative on IT and mobile communication, Jg. 76 (2013), Heft 3, S. 353-366
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Zugriff:
This paper presents a 3rd-order, 3-bit continuous-time (CT) \Updelta\Upsigma Δ Σ modulator for an LTE radio receiver. A return-to-zero (RZ) pulse, centered in the sampling period by a quadrature clock, is used in the innermost DAC to reduce the sensitivity to loop-delay variations in the modulator, and omit implementing the additional loop delay compensation usually needed in CT modulators. The performance and stability of the NRZ/NRZ/RZ feedback scheme is thoroughly analysed using a discrete-time model. The modulator has been implemented in a 65 nm CMOS process, where it occupies an area of 0.2 × 0.4 mm2. It achieves an SNR of 71 dB and an SNDR of 69 dB over a 9 MHz bandwidth with an oversampling ratio of 16, and a power consumption of 7.5 mW from a 1.2 V supply.
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Theory and Design of a CT Delta Sigma Modulator with Low Sensitivity to Loop-Delay Variations
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Autor/in / Beteiligte Person: | Andersson, Mattias ; Sundström, Lars ; Andersson, Martin ; Andreani, Pietro |
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Zeitschrift: | Analog Integrated Circuits and Signal Processing ELLIIT: the Linköping-Lund initiative on IT and mobile communication, Jg. 76 (2013), Heft 3, S. 353-366 |
Veröffentlichung: | 2013 |
Medientyp: | unknown |
ISSN: | 0925-1030 (print) |
DOI: | 10.1007/s10470-013-0114-y |
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