High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding
In: IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, 2013, S. 58-59
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Zugriff:
Binary Signed-Digit Residue Number System (BSD-RNS) has been proposed in the literatures as an appropriate number system to perform the arithmetic operations in parallel. BSD-RNS addition is the basic operation and improving its performance results in efficient VLSI arithmetic circuits. Here, we present a new architecture for carry-free BSD-RNS addition utilizing a recently proposed posibit and negabit BSD representation. Compared to 2's complement BSD-RNS adder, the proposed architecture has 21% less delay. Besides, for a same delay (0.6ns), we obtain 48% less area and 28% less power than the most efficient existing BSD-RNS adder.
| Titel: |
High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding
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| Autor/in / Beteiligte Person: | Timarchi, S. ; Saremi, M. ; Fazlali, M. ; Gaydadjiev, Georgi |
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| Zeitschrift: | IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, 2013, S. 58-59 |
| Veröffentlichung: | 2013 |
| Medientyp: | unknown |
| ISBN: | 1-4799-0524-0 (print) ; 978-1-4799-0524-9 (print) |
| ISSN: | 2324-8440 (print) ; 2324-8432 (print) |
| DOI: | 10.1109/VLSI-SoC.2013.6673248 |
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